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36 Open 232 Closed
36 Open 232 Closed
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Issues list

Debug entry during hardware vectoring.
#428 opened Oct 14, 2024 by MarkHillCodasip
Spec doesn't say to clear the second lowest bit of trap handler addresses v1.0 resolve for 1.0
#427 opened Oct 14, 2024 by Timmmm
@jb-brelot-nxp
In Appendix, we should not have CLIC interrupt ID recommendation chapter. v1.0 resolve for 1.0
#426 opened Oct 7, 2024 by jb-brelot-nxp
@james-ball-qualcomm
clicintattr.mode should not be writable from S-mode v1.0 resolve for 1.0
#424 opened Oct 4, 2024 by christian-herber-nxp
@jb-brelot-nxp
1
Scratch Swap CSR (sscratchcswl) CSR section missing in ssclic chapter v1.0 resolve for 1.0
#422 opened Sep 30, 2024 by james-ball-qualcomm
@jb-brelot-nxp
The smclicshv extension naming (i.e. sm*) suggests it only has M-mode features but it affects S-mode and has one S-mode CSR bit reorg Reorganization for Priv ISA manual integration v1.0 resolve for 1.0
#421 opened Sep 30, 2024 by james-ball-qualcomm
@jb-brelot-nxp
4
Recommend moving definition of indirect CSRs into their own chapter and clarifying they are accessed via M-mode or S-mode CSRs. reorg Reorganization for Priv ISA manual integration v1.0 resolve for 1.0
#420 opened Sep 30, 2024 by james-ball-qualcomm
@christian-herber-nxp
2
Inconsistency on which fields are zeroed when switching to CLINT mode v1.0 resolve for 1.0
#418 opened Sep 24, 2024 by Timmmm
@james-ball-qualcomm
Simplify and fully specify xscratchcsw[l] v1.0 resolve for 1.0
#416 opened Sep 23, 2024 by Timmmm
@james-ball-qualcomm
Write side-effects for csrrs rd, mnxti, rs1 when rs1 is not x0 v1.0 resolve for 1.0
#415 opened Sep 18, 2024 by MarkHillCodasip
@jb-brelot-nxp
1
Move register layout definitions into wavedrom v1.0 resolve for 1.0
#414 opened Sep 17, 2024 by christian-herber-nxp
@wmat @jb-brelot-nxp
6
Explicitly list dependence on Smcsrind/Sscsrind v1.0 resolve for 1.0
#412 opened Sep 12, 2024 by christian-herber-nxp
@james-ball-qualcomm
The text definition of xscratchcswl is incomplete v1.0 resolve for 1.0
#407 opened Sep 11, 2024 by Timmmm
@james-ball-qualcomm
1
xscratchcswl privilege behaviour not fully specified v1.0 resolve for 1.0
#406 opened Sep 11, 2024 by Timmmm
@james-ball-qualcomm
2
Clarify behaviour of xnxti register version in smclicshv v1.0 resolve for 1.0
#402 opened Aug 27, 2024 by jakubahh
@jb-brelot-nxp
1
Make shv a per level property post-v1.0 To be handled after v1.0
#400 opened Aug 15, 2024 by christian-herber-nxp
@jb-brelot-nxp
1
an exception trap on the trap handler function address fetch cannot return to the instruction interrupted (smclicshv) v1.0 resolve for 1.0
#399 opened Jul 15, 2024 by hirooih
@james-ball-qualcomm
Questions on Release 0.9 v1.0 resolve for 1.0
#398 opened Jul 15, 2024 by hirooih
@jb-brelot-nxp
Missing a catchy terminology for the selection priority post-v1.0 To be handled after v1.0
#396 opened May 16, 2024 by christian-herber-nxp
@jb-brelot-nxp
6
Require immediate evaluation of clicintie and clicintip v1.0 resolve for 1.0
#378 opened Mar 5, 2024 by Silabs-ArjanB
@james-ball-qualcomm
13
How should non-normative text be specified in CLIC spec v1.0 resolve for 1.0
#376 opened Mar 5, 2024 by christian-herber-nxp
5
xcause.inhv conflicts with enabling CLIC per mode post-v1.0 To be handled after v1.0
#348 opened Aug 18, 2023 by JamesKenneyImperas
2
Add optional support for hardware register save e.g. shadow register sets? post-v1.0 To be handled after v1.0
#329 opened Apr 23, 2023 by brucehoult
3
Hypervisor mode should be discussed. post-v1.0 To be handled after v1.0
#248 opened Jun 21, 2022 by kasanovic
2
is spike support required? post-v1.0 To be handled after v1.0
#242 opened May 24, 2022 by dansmathers
4
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