Debug entry during hardware vectoring.

[MarkHillCodasip]

Specification says that:

In CLIC mode, the dpc CSR additionally may hold the faulting address if breakpoints are allowed to trap on the table fetch during hardware vectoring. If breakpoints are allowed to trap on the table read, dret should honor xinhv.

However, I don't think xinhv can be used for this purpose because as well as being set during the implicit vector table fetch it will also be set if debug mode is entered while in the middle of executing a fault handler on a failed vector table fetch. In this situation xinhv will be set but dpc will not be pointing to a trap vector table entry.

If debug mode can be entered with dpc pointing to a trap vector table entry I think the debug state needs its own inhv bit to indicate that.