soc: riscv: andes_v5: update ae350 soc #59813

jimmyzhe · 2023-06-28T10:47:23Z

This PR refines ae350 porting and adds some Andes features below.

Refine exist code:
- AE350 linker script
- PMA driver
- L2 cache driver
Enable RISC-V feature on AE350:
- PMP
- RV32E
- C extension
Add Andes feature:
- EXEC.IT (Execution on Instruction Table )
  EXEC.IT is supported by Andes V5 toolchain which generates a look-up table and replaces suitable 32-bit instructions with the 16-bit exec.it instruction to decrease code size.
- IOCP (I/O Coherence Port)
  IOCP handle cache coherency between cache and external non-caching master, such DMA controller.

carlocaione · 2023-06-30T08:32:36Z

soc/riscv/riscv-privileged/andes_v5/ae350/linker.ld

are the changes in this file valid in general for all the RISCV boards or just for Andes?

The difference between RISC-V generic linker.ld and ae350 linker.ld is as follows:

apply MPU_ALIGN to __rom_region_start and __rom_region_end (for XIP only).

redefine MPU_ALIGN to match the granularity of PMA

I think (1) applies to all RISC-V boards, while (2) is specific to Andes boards.

carlocaione · 2023-06-30T08:33:40Z

soc/riscv/riscv-privileged/andes_v5/Kconfig.soc

@@ -28,6 +28,12 @@ config RV32I_CPU
 	select RISCV_ISA_EXT_ZICSR
 	select RISCV_ISA_EXT_ZIFENCEI

+config RV32E_CPU


We already have CONFIG_RISCV_ISA_RV32E, why this is needed?

AE350 is FPGA based platform and we want RV32E can be selected by
menuconfig or board_defconfig for AE350 bitstream integrate with RV32E core.

carlocaione · 2023-06-30T08:34:51Z

soc/riscv/riscv-privileged/andes_v5/l2_cache.c

+		/* Memory barrier, flush all I/D-Cache before setting L2C */
+		__asm__ volatile ("fence.i");


Please use the newly introduced barrier API for this. See include/zephyr/sys/barrier.h

Andes core needs to execute fence.i to flush all I/D cache before updating the L2 cache function.
The barrier API in RISC-V seems only support fence instruction.
Maybe I can modify the comment to avoid confusion.

Right but why you cannot use fence here instead of fence.i? AFAIK fence should be just a bit more restrictive.

In Andes core, fence instruction is used to order device I/O and memory accesses as viewed by other RISC-V harts and external devices, but it does not perform any operation on the local I/D cache.
fence.i is used to synchronizing the L1 and L2 cache due to the hardware limitation of Andes L2 cache.

fkokosinski · 2023-06-30T09:26:20Z

boards/riscv/adp_xc7k_ae350/adp_xc7k_ae350_defconfig

 # HW DSP options
 #CONFIG_SOC_ANDES_V5_HWDSP=y

+# EXEC.IT options
+#CONFIG_SOC_ANDES_V5_EXECIT=y


Why is this commented out?

Only Andes toolchain support this option, disable this option for zephyr-sdk.

fkokosinski · 2023-06-30T09:26:27Z

boards/riscv/adp_xc7k_ae350/adp_xc7k_ae350_defconfig

 # Cache options
 CONFIG_CACHE_ENABLE=y

 # Nocache memory options
 #CONFIG_SOC_ANDES_V5_PMA=y
 #CONFIG_NOCACHE_MEMORY=y
+
+# I/O Coherence Port options
+#CONFIG_SOC_ANDES_V5_IOCP=y


Not all of AE350 bitstream support IOCP, disable this option for various AE350 bitstream compatible.

fkokosinski · 2023-06-30T09:33:24Z

soc/riscv/riscv-privileged/andes_v5/pma.c

 	case 15:
-		write_csr(NDS_PMAADDR15, value); break;
+		csr_write(NDS_PMAADDR15, value); break;


Looks like a lot of repeated code. Can you generate it with FOR_EACH helper macro?

Nice suggestion, fixed it, thank you.

fkokosinski · 2023-06-30T09:33:42Z

soc/riscv/riscv-privileged/andes_v5/pma.c

 	case 3:
-		read_csr(pmacfg, NDS_PMACFG3); break;
+		pmacfg = csr_read(NDS_PMACFG3); break;


Ditto - FOR_EACH could help reduce the repeated code.

fkokosinski · 2023-06-30T09:33:58Z

soc/riscv/riscv-privileged/andes_v5/pma.c

 	case 3:
-		write_csr(NDS_PMACFG3, pmacfg); break;
+		csr_write(NDS_PMACFG3, pmacfg); break;


Ditto - FOR_EACH could help reduce the repeated code.

Fix mtimer lack of interrupts-extended and make syscon compatilbe to atcsmu100. Signed-off-by: Jimmy Zheng <[email protected]>

Synchronize ae350 linker.ld with riscv generic linker.ld and workaround kernel object address may be 0x0 in XIP system. Signed-off-by: Jimmy Zheng <[email protected]>

Refine PMA driver and define MPU_ALIGN() to PMA granularity in RAM_SECTIONS, otherwise MPU_ALIGN() is defined to PMP granularity. Signed-off-by: Jimmy Zheng <[email protected]>

Enable PMP and set PMP granularity to 8 for most of ae350 bitstream. This commit also make MPU_ALIGN() apply to __rom_region_end in XIP system. Signed-off-by: Jimmy Zheng <[email protected]>

Enable RISC-V C extension for Andes core. Signed-off-by: Jimmy Zheng <[email protected]>

Add CONFIG_RV32E_CPU for AE350 platform integrated with Andes RV32E core, such as N22, D23 core. Signed-off-by: Jimmy Zheng <[email protected]>

Andes EXEC.IT (Execution on Instruction Table) is supported by Andes toolchain only. Andes toolchain will replaces suitable 32-bit instructions with the 16-bit "exec.it <INDEX>" in which <INDEX> points to a corresponding 32-bit instruction in look up table. Signed-off-by: Jimmy Zheng <[email protected]>

Refine source code and flush all I/D-Cache before update L2 cache register. Signed-off-by: Jimmy Zheng <[email protected]>

Add CONFIG_SOC_ANDES_V5_IOCP to indicate Andes I/O Coherence Port handle cache coherency between cache and external non-caching master, such as DMA controller. Signed-off-by: Jimmy Zheng <[email protected]>

Enlarge TEST_EXTRA_STACK_SIZE for AE350 RV64 bitstream. Signed-off-by: Jimmy Zheng <[email protected]>

Exclude adp_xc7k_ae350 because Andes core doesn't support RISC-V vectored mode from csr $mtvec. Signed-off-by: Jimmy Zheng <[email protected]>

Replace redundant CONFIG_CACHE_ENABLE by generic Kconfig CONFIG_ICACHE, CONFIG_DCACHE. Signed-off-by: Jimmy Zheng <[email protected]>

jimmyzhe · 2023-07-03T02:26:18Z

Based on the conversation in #59041, I have removed the redundant Kconfig CONFIG_CACHE_ENABLE, thank you @carlocaione for your comment.

carlocaione

In general LGTM. I cannot vouch for the soc-specific changes but being self-contained in the soc/board directories I'm ok with that.

jimmyzhe requested review from dcpleung, andyross and nashif as code owners June 28, 2023 10:47

zephyrbot added area: Kernel area: RISCV RISCV Architecture (32-bit & 64-bit) labels Jun 28, 2023

zephyrbot requested review from carlocaione, ceolin, edersondisouza, fkokosinski, katsuster, kgugala, mgielda, peter-mitsis and tgorochowik June 28, 2023 10:47

zephyrbot assigned fkokosinski Jun 28, 2023

jimmyzhe force-pushed the update_andes_v5 branch from e942f6b to b71ee0f Compare June 28, 2023 11:07

carlocaione requested changes Jun 30, 2023

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fkokosinski reviewed Jun 30, 2023

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jimmyzhe added 12 commits July 3, 2023 09:31

dts: riscv: andes_v5: update andes_v5_ae350.dtsi

5f2a431

Fix mtimer lack of interrupts-extended and make syscon compatilbe to atcsmu100. Signed-off-by: Jimmy Zheng <[email protected]>

soc: riscv: andes_v5: update ae350 linker.ld

503ec4e

Synchronize ae350 linker.ld with riscv generic linker.ld and workaround kernel object address may be 0x0 in XIP system. Signed-off-by: Jimmy Zheng <[email protected]>

soc: riscv: andes_v5: refine Andes PMA

b38e403

Refine PMA driver and define MPU_ALIGN() to PMA granularity in RAM_SECTIONS, otherwise MPU_ALIGN() is defined to PMP granularity. Signed-off-by: Jimmy Zheng <[email protected]>

soc: riscv: andes_v5: support PMP and USERSPACE

d5c05c3

Enable PMP and set PMP granularity to 8 for most of ae350 bitstream. This commit also make MPU_ALIGN() apply to __rom_region_end in XIP system. Signed-off-by: Jimmy Zheng <[email protected]>

soc: riscv: andes_v5: support RISC-V C extension

9874e6b

Enable RISC-V C extension for Andes core. Signed-off-by: Jimmy Zheng <[email protected]>

soc: riscv: andes_v5: add RV32E_CPU option

2c2ae3a

Add CONFIG_RV32E_CPU for AE350 platform integrated with Andes RV32E core, such as N22, D23 core. Signed-off-by: Jimmy Zheng <[email protected]>

soc: riscv: andes_v5: refine Andes L2 cache

c1f6128

Refine source code and flush all I/D-Cache before update L2 cache register. Signed-off-by: Jimmy Zheng <[email protected]>

soc: riscv: andes_v5: add Andes I/O Coherence Port option

ce78cab

Add CONFIG_SOC_ANDES_V5_IOCP to indicate Andes I/O Coherence Port handle cache coherency between cache and external non-caching master, such as DMA controller. Signed-off-by: Jimmy Zheng <[email protected]>

soc: riscv: andes_v5: enlarge TEST_EXTRA_STACK_SIZE

c730720

Enlarge TEST_EXTRA_STACK_SIZE for AE350 RV64 bitstream. Signed-off-by: Jimmy Zheng <[email protected]>

tests: kernel: gen_isr_table.riscv_direct: exclude adp_xc7k_ae350

b4bafec

Exclude adp_xc7k_ae350 because Andes core doesn't support RISC-V vectored mode from csr $mtvec. Signed-off-by: Jimmy Zheng <[email protected]>

soc: riscv: andes_v5: remove redundant CONFIG_CACHE_ENABLE

7f75156

Replace redundant CONFIG_CACHE_ENABLE by generic Kconfig CONFIG_ICACHE, CONFIG_DCACHE. Signed-off-by: Jimmy Zheng <[email protected]>

jimmyzhe force-pushed the update_andes_v5 branch from b71ee0f to 7f75156 Compare July 3, 2023 02:10

jimmyzhe requested review from carlocaione and fkokosinski July 10, 2023 01:48

carlocaione approved these changes Jul 11, 2023

View reviewed changes

fkokosinski approved these changes Jul 17, 2023

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fabiobaltieri merged commit 4f26203 into zephyrproject-rtos:main Jul 17, 2023
18 checks passed

jimmyzhe deleted the update_andes_v5 branch July 18, 2023 01:20

jimmyzhe mentioned this pull request Sep 20, 2024

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soc: riscv: andes_v5: update ae350 soc #59813

soc: riscv: andes_v5: update ae350 soc #59813

jimmyzhe commented Jun 28, 2023

carlocaione Jun 30, 2023

jimmyzhe Jul 3, 2023 •

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jimmyzhe commented Jul 3, 2023

carlocaione left a comment

		/* Memory barrier, flush all I/D-Cache before setting L2C */
		__asm__ volatile ("fence.i");

soc: riscv: andes_v5: update ae350 soc #59813

soc: riscv: andes_v5: update ae350 soc #59813

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