soc: riscv: andes_v5: remove redundant CONFIG_CACHE_ENABLE

Replace redundant CONFIG_CACHE_ENABLE by generic Kconfig CONFIG_ICACHE, CONFIG_DCACHE. Signed-off-by: Jimmy Zheng <[email protected]>
zephyrproject-rtos · Jul 17, 2023 · 4f26203 · 4f26203
1 parent 82c2f38
commit 4f26203
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Showing 4 changed files with 14 additions and 14 deletions.
diff --git a/boards/riscv/adp_xc7k_ae350/adp_xc7k_ae350_defconfig b/boards/riscv/adp_xc7k_ae350/adp_xc7k_ae350_defconfig
@@ -42,9 +42,6 @@ CONFIG_PMP_GRANULARITY=8
 # EXEC.IT options
 #CONFIG_SOC_ANDES_V5_EXECIT=y
 
-# Cache options
-CONFIG_CACHE_ENABLE=y
-
 # Nocache memory options
 #CONFIG_SOC_ANDES_V5_PMA=y
 #CONFIG_NOCACHE_MEMORY=y

diff --git a/soc/riscv/riscv-privileged/andes_v5/Kconfig.defconfig.ae350 b/soc/riscv/riscv-privileged/andes_v5/Kconfig.defconfig.ae350
@@ -7,7 +7,7 @@ config SOC
 	default "ae350"
 
 config SYS_CLOCK_TICKS_PER_SEC
-	default 100 if (!CACHE_ENABLE || XIP)
+	default 100 if (!ICACHE || XIP)
 
 config MAIN_STACK_SIZE
 	default 2048

diff --git a/soc/riscv/riscv-privileged/andes_v5/Kconfig.soc b/soc/riscv/riscv-privileged/andes_v5/Kconfig.soc
@@ -12,6 +12,8 @@ config SOC_RISCV_ANDES_AE350
 	select RISCV_ISA_EXT_M
 	select RISCV_ISA_EXT_A
 	select RISCV_ISA_EXT_C
+	select CPU_HAS_DCACHE
+	select CPU_HAS_ICACHE
 	select RISCV_PMP
 
 endchoice
@@ -60,10 +62,6 @@ config DOUBLE_PRECISION_FPU
 
 endchoice
 
-config CACHE_ENABLE
-	bool "Cache"
-	default n
-
 config SOC_ANDES_V5_HWDSP
 	bool "AndeStar V5 DSP ISA"
 	select RISCV_SOC_CONTEXT_SAVE
@@ -117,7 +115,7 @@ config SOC_ANDES_V5_L2C
 config SOC_ANDES_V5_IOCP
 	bool "Andes V5 I/O Coherence Port (IOCP)"
 	depends on SOC_ANDES_V5_L2C
-	depends on CACHE_ENABLE
+	depends on DCACHE
 	help
 		Support Andes V5 I/O Coherence Port to handle cache coherency
 		between cache and external non-caching master, such as DMA

diff --git a/soc/riscv/riscv-privileged/andes_v5/start.S b/soc/riscv/riscv-privileged/andes_v5/start.S
@@ -21,15 +21,20 @@ SECTION_FUNC(init, entry)
 	csrw NDS_UITB, t0
 #endif
 
-#ifdef CONFIG_CACHE_ENABLE
+#ifdef CONFIG_ICACHE
+	/* Enable I cache with HW prefetcher. */
+	li t0, (1 << 9) | (1 << 0)
+	csrs NDS_MCACHE_CTL, t0
+#endif
+
+#ifdef CONFIG_DCACHE
 	/*
-	 * Enable I/D cache with HW prefetcher,
-	 * D-cache write-around (threshold: 4 cache lines),
-	 * and CM (Coherence Manager).
+	 * Enable D cache with HW prefetcher, D-cache write-around
+	 * (threshold: 4 cache lines), and CM (Coherence Manager).
 	 */
 	li t0, (0x3 << 13)
 	csrc NDS_MCACHE_CTL, t0
-	li t0, (1 << 19) | (1 << 13) | (1 << 10) | (1 << 9) | (0x3)
+	li t0, (1 << 19) | (1 << 13) | (1 << 10) | (1 << 1)
 	csrs NDS_MCACHE_CTL, t0
 
 	/* Check if CPU support CM or not. */