tests: kernel: gen_isr_table.riscv_direct: exclude adp_xc7k_ae350

Exclude adp_xc7k_ae350 because Andes core doesn't support RISC-V vectored mode from csr $mtvec. Signed-off-by: Jimmy Zheng <[email protected]>
zephyrproject-rtos · Jun 28, 2023 · b71ee0f · b71ee0f
1 parent abce0eb
commit b71ee0f
Showing 1 changed file with 3 additions and 1 deletion.
diff --git a/tests/kernel/gen_isr_table/testcase.yaml b/tests/kernel/gen_isr_table/testcase.yaml
@@ -50,7 +50,9 @@ tests:
     arch_allow:
       - riscv32
       - riscv64
-    platform_exclude: m2gl025_miv
+    platform_exclude:
+      - m2gl025_miv
+      - adp_xc7k_ae350
     filter: CONFIG_SOC_FAMILY_RISCV_PRIVILEGED
     extra_configs:
       - CONFIG_GEN_IRQ_VECTOR_TABLE=y