soc: riscv: andes_v5: update ae350 soc #59813
Commits on Jul 3, 2023
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dts: riscv: andes_v5: update andes_v5_ae350.dtsi
Fix mtimer lack of interrupts-extended and make syscon compatilbe to atcsmu100. Signed-off-by: Jimmy Zheng <[email protected]>
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soc: riscv: andes_v5: update ae350 linker.ld
Synchronize ae350 linker.ld with riscv generic linker.ld and workaround kernel object address may be 0x0 in XIP system. Signed-off-by: Jimmy Zheng <[email protected]>
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soc: riscv: andes_v5: refine Andes PMA
Refine PMA driver and define MPU_ALIGN() to PMA granularity in RAM_SECTIONS, otherwise MPU_ALIGN() is defined to PMP granularity. Signed-off-by: Jimmy Zheng <[email protected]>
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soc: riscv: andes_v5: support PMP and USERSPACE
Enable PMP and set PMP granularity to 8 for most of ae350 bitstream. This commit also make MPU_ALIGN() apply to __rom_region_end in XIP system. Signed-off-by: Jimmy Zheng <[email protected]>
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soc: riscv: andes_v5: support RISC-V C extension
Enable RISC-V C extension for Andes core. Signed-off-by: Jimmy Zheng <[email protected]>
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soc: riscv: andes_v5: add RV32E_CPU option
Add CONFIG_RV32E_CPU for AE350 platform integrated with Andes RV32E core, such as N22, D23 core. Signed-off-by: Jimmy Zheng <[email protected]>
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soc: riscv: andes_v5: add Andes EXEC.IT option
Andes EXEC.IT (Execution on Instruction Table) is supported by Andes toolchain only. Andes toolchain will replaces suitable 32-bit instructions with the 16-bit "exec.it <INDEX>" in which <INDEX> points to a corresponding 32-bit instruction in look up table. Signed-off-by: Jimmy Zheng <[email protected]>
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soc: riscv: andes_v5: refine Andes L2 cache
Refine source code and flush all I/D-Cache before update L2 cache register. Signed-off-by: Jimmy Zheng <[email protected]>
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soc: riscv: andes_v5: add Andes I/O Coherence Port option
Add CONFIG_SOC_ANDES_V5_IOCP to indicate Andes I/O Coherence Port handle cache coherency between cache and external non-caching master, such as DMA controller. Signed-off-by: Jimmy Zheng <[email protected]>
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soc: riscv: andes_v5: enlarge TEST_EXTRA_STACK_SIZE
Enlarge TEST_EXTRA_STACK_SIZE for AE350 RV64 bitstream. Signed-off-by: Jimmy Zheng <[email protected]>
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tests: kernel: gen_isr_table.riscv_direct: exclude adp_xc7k_ae350
Exclude adp_xc7k_ae350 because Andes core doesn't support RISC-V vectored mode from csr $mtvec. Signed-off-by: Jimmy Zheng <[email protected]>
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soc: riscv: andes_v5: remove redundant CONFIG_CACHE_ENABLE
Replace redundant CONFIG_CACHE_ENABLE by generic Kconfig CONFIG_ICACHE, CONFIG_DCACHE. Signed-off-by: Jimmy Zheng <[email protected]>
