#

asic-design

Here are 64 public repositories matching this topic...

chipsalliance / Cores-VeeR-EH1

VeeR EH1 core

fpga processor riscv rtl risc risc-v open-source-hardware fusesoc verilator riscv32 western-digital axi4 ahb-lite asic-design veer

Updated May 29, 2023
SystemVerilog

hughperkins / VeriGPU

OpenSource GPU, in Verilog, loosely based on RISC-V ISA

machine-learning gpu verification verilog gpu-acceleration hardware-designs risc-v asic-design risc-v-assembly

Updated Jun 21, 2024
SystemVerilog

google / qkeras

QKeras: a quantization deep learning library for Tensorflow Keras

machine-learning fpga deep-learning tensorflow accelerator keras quantization hardware-acceleration fpga-accelerator quantized-neural-networks asic-design quantized-networks

Updated Oct 23, 2024
Python

dpretet / async_fifo

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

asic fpga async verification verilog synthesis icarus-verilog fifo cdc hdl verilog-hdl fifo-queue fifo-cache verilator asic-design cross-clock-domain

Updated Apr 30, 2024
Verilog

chipsalliance / Cores-VeeR-EL2

VeeR EL2 Core

fpga processor riscv rtl risc-v open-source-hardware fusesoc verilator riscv32 western-digital axi4 ahb-lite asic-design el2

Updated Oct 31, 2024
SystemVerilog

stnolting / neoTRNG

🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).

cryptography asic fpga entropy random vhdl chaos rtl rng random-number-generators hdl key-generator trng entropy-source ring-oscillator asic-design neorv32

Updated Oct 26, 2024
VHDL

lirui-shanghaitech / CNN-Accelerator-VLSI

Convolutional accelerator kernel, target ASIC & FPGA

fpga accelerator cnn fpga-accelerator cnn-digital cnn-accelerator asic-design

Updated Apr 10, 2023
Verilog

abdelazeem201 / Systolic-array-implementation-in-RTL-for-TPU

IC implementation of Systolic Array for TPU

asic fpga rtl verilog asic-verification asic-design

Updated Oct 21, 2024
Verilog

cpc / openasip

Open Application-Specific Instruction Set processor tools (OpenASIP)

fpga hardware-designs asic-design hardware-accelerators

Updated Apr 24, 2024
C

AUCOHL / DFFRAM

Standard Cell Library based Memory Compiler using FF/Latch cells

verilog vlsi vlsi-physical-design vlsi-circuits electronics-design asic-design

Updated Jun 15, 2024
Verilog

dpretet / axi-crossbar

An AXI4 crossbar implementation in SystemVerilog

arm asic fpga processor riscv verilog soc fpga-soc interconnect amba crossbar riscv32 axi4 axi4-lite riscv64 monodraw axi4-protocol asic-design axi4-full

Updated May 28, 2024
SystemVerilog

thousrm / universal_NPU-CNN_accelerator

hardware design of universal NPU(CNN accelerator) for various convolution neural network

cnn verilog npu cnn-accelerator asic-design hardware-design

Updated Oct 30, 2024
Verilog

cgra4ml

KastnerRG / cgra4ml

An Open Workflow to Build Custom SoCs and run Deep Models at the Edge

asic ai fpga neural-network cnn dnn verilog systemverilog axi-stream asic-design hls4ml

Updated Aug 3, 2024
SystemVerilog

abdelazeem201 / Design-and-ASIC-Implementation-of-32-Point-FFT-Processor

I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be …

asic fpga vhdl rtl verilog synthesis fft soc asic-verification asic-design

Updated Dec 3, 2023
Verilog

JeffDeCola / my-verilog-examples

A place to keep my synthesizable verilog examples.

simulator asic fpga hardware waveform verilog xilinx synthesis vivado systemverilog gtkwave hdl iverilog hardware-description-language verilog-simulator asic-design synthesize hardware-architecture

Updated Jul 10, 2023
Verilog

lethalbit / kicad-pdk-libs

KiCad symbol library for sky130 and gf180mcu PDKs

electronics spice kicad asic-design

Updated Feb 14, 2024
Python

Lampro-Mellon / Quasar

Quasar 2.0: Chisel equivalent of SweRV-EL2

scala processor chisel riscv rtl chisel3 open-source-hardware verilator asic-verification axi4 ahb-lite asic-design swerv swerv-el2

Updated Apr 13, 2021
Scala

dpretet / friscv

RISCV CPU implementation in SystemVerilog

asic fpga assembler riscv verilog systemverilog fpga-soc risc-v rv32i crossbar axi4 axi4-protocol asic-design riscv-cpu

Updated Oct 8, 2024
SystemVerilog

sdnellen / open-register-design-tool

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

eda verilog systemverilog uvm registers systemrdl register-descriptions systemrdl-compiler fpga-development asic-design

Updated Oct 21, 2024
Verilog

OrsuVenkataKrishnaiah1235 / RTL-Coding

"Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"

fpga vhdl rtl verilog hdlbits asic-design rtl-design-and-verification rtl-coding hdlbitssolution

Updated Aug 13, 2023
Verilog

Improve this page

Add a description, image, and links to the asic-design topic page so that developers can more easily learn about it.

Curate this topic

Add this topic to your repo

To associate your repository with the asic-design topic, visit your repo's landing page and select "manage topics."