Skip to content
@chipsalliance

CHIPS Alliance

Common Hardware for Interfaces, Processors and Systems
README.md

CHIPS Alliance Logo

🔗 chipsalliance.org | 📫 [email protected]

The CHIPS Alliance develops high-quality, open source hardware designs and tools relevant to ASICs and FPGAs. By creating an open and collaborative environment, CHIPS Alliance shares resources to lower the cost of development. Companies and individuals can work together to develop open source CPUs, various peripherals, and complex IP blocks, as well as open source hardware or software tools to accelerate the creation of more efficient and innovative chip designs.

The CHIPS Alliance hosts multiple open source Projects, which are Workgroups.

Popular repositories Loading

  1. chisel chisel Public

    Chisel: A Modern Hardware Design Language

    Scala 3.9k 588

  2. rocket-chip rocket-chip Public

    Rocket Chip Generator

    Scala 3.2k 1.1k

  3. verible verible Public

    Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

    C++ 1.3k 200

  4. riscv-dv riscv-dv Public

    Random instruction generator for RISC-V processor verification

    Python 1k 322

  5. Cores-VeeR-EH1 Cores-VeeR-EH1 Public

    VeeR EH1 core

    SystemVerilog 810 219

  6. firrtl firrtl Public archive

    Flexible Intermediate Representation for RTL

    Scala 720 175

Repositories

Showing 10 of 107 repositories
  • verible Public

    Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

    chipsalliance/verible’s past year of commit activity
    C++ 1,325 200 466 (15 issues need help) 22 Updated Sep 20, 2024
  • sv-tests Public

    Test suite designed to check compliance with the SystemVerilog standard.

    chipsalliance/sv-tests’s past year of commit activity
    SystemVerilog 284 ISC 75 45 (5 issues need help) 22 Updated Sep 20, 2024
  • aib-phy-hardware Public

    Advanced Interface Bus (AIB) die-to-die hardware open source

    chipsalliance/aib-phy-hardware’s past year of commit activity
    Verilog 118 Apache-2.0 29 0 0 Updated Sep 20, 2024
  • caliptra-sw Public

    Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test

    chipsalliance/caliptra-sw’s past year of commit activity
    Rust 51 Apache-2.0 39 84 54 Updated Sep 19, 2024
  • chisel-nix Public

    Nix scripts used to manage the chisel projects.

    chipsalliance/chisel-nix’s past year of commit activity
    Nix 20 1 0 2 Updated Sep 19, 2024
  • caliptra-rtl Public

    HW Design Collateral for Caliptra RoT IP

    chipsalliance/caliptra-rtl’s past year of commit activity
    SystemVerilog 65 Apache-2.0 36 66 10 Updated Sep 19, 2024
  • caliptra-ss Public

    HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.

    chipsalliance/caliptra-ss’s past year of commit activity
    SystemVerilog 3 Apache-2.0 1 11 1 Updated Sep 19, 2024
  • chisel Public

    Chisel: A Modern Hardware Design Language

    chipsalliance/chisel’s past year of commit activity
    Scala 3,919 Apache-2.0 588 306 (1 issue needs help) 155 Updated Sep 19, 2024
  • Surelog Public

    SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

    chipsalliance/Surelog’s past year of commit activity
    C++ 354 Apache-2.0 68 48 (2 issues need help) 0 Updated Sep 19, 2024
  • Cores-VeeR-EL2 Public

    VeeR EL2 Core

    chipsalliance/Cores-VeeR-EL2’s past year of commit activity
    SystemVerilog 244 Apache-2.0 73 20 6 Updated Sep 19, 2024
View all repositories