Merge `CVA6Cfg` and `ArianeCfg` #1321

zarubaf · 2023-07-26T11:10:19Z

This commit merges these two similar strategies for parameterization. A further step towards the clean-up.

@Jbalkind I haven't adapted the OpenPiton wrapper so that will break for sure. Not sure how you'd like to proceed but probably it makes the most sense to adapt that once and for all, instead of incremental. Also see the new enum type, ~~I also have removed SwapEndianess since I haven't seen a use-case for that anymore (it was set to 1 in the OP config). I might have missed the underlying nature, so please do let me know.~~

How has that been tested?

Running dhrystone before and after the merge.

Fixes #1319

corev_apu/tb/ariane_soc_pkg.sv

Jbalkind · 2023-07-26T13:24:11Z

Two things:

Can you please not remove the swapendianness thing? This affects decision making for CV-Mesh and I'd rather leave it in there until we're sure we don't need it
Can we call it L1 protocol or something instead of bus type? We already call the type noc_*_t

zarubaf · 2023-07-26T13:35:26Z

Two things:

Can you please not remove the swapendianness thing? This affects decision making for CV-Mesh and I'd rather leave it in there until we're sure we don't need it

Can we call it L1 protocol or something instead of bus type? We already call the type noc_*_t

Should be fixed, please re-check. I've renamed it to noc_type_e which is in line with the noc ports.

Jbalkind · 2023-07-26T13:40:18Z

Ok I see what you did - seems fine from my perspective :) Thanks!

github-actions · 2023-07-26T14:32:45Z

❌ failed run, report available here.

JeanRochCoulon

Very good proposal !! I approve

JeanRochCoulon · 2023-07-26T16:59:49Z

corev_apu/tb/ariane_testharness.sv

-    unsigned'(cva6_config_pkg::CVA6ConfigAxiIdWidth),     // AxiIdWidth
-    unsigned'(cva6_config_pkg::CVA6ConfigDataUserWidth)   // AxiUserWidth
-  },
+  parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_soc::CVA6SoCCfg,


Why not replacing it by:
parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_pkg::CVA6Cfg
and remove the arien_soc::CVA6SocCfg definition ?
To avoid duplication

That would create a dependency again from the soc into the main core, memory regions are inherently tied to the SoC which is using the core and I want to keep those as part of the SoC package (if that makes sense). I think we need to live with this duplication here :/

JeanRochCoulon · 2023-07-26T17:00:34Z

corev_apu/tb/ariane_tb.sv

-        unsigned'(cva6_config_pkg::CVA6ConfigAxiDataWidth),   // AxiDataWidth
-        unsigned'(cva6_config_pkg::CVA6ConfigAxiIdWidth),     // AxiIdWidth
-        unsigned'(cva6_config_pkg::CVA6ConfigDataUserWidth)   // AxiUserWidth
-    };
    localparam type rvfi_instr_t = struct packed {


I think vcs-testharness regression will fail if CVA6Cfg is not defined in arien_tb module.

github-actions · 2023-07-26T19:57:10Z

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github-actions · 2023-07-28T09:06:27Z

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ASintzoff · 2023-08-01T13:38:48Z

@zarubaf is there any fix for errors raised by the FPGA job?

ERROR: [Synth 8-6038] cannot resolve hierarchical name for the item 'valid' [/gitlab-runner/riscv-public/builds/21Uxzs_1/8/riscv-ci/cva6/core/cva6.sv:1145]
ERROR: [Synth 8-660] unable to resolve 'ENV_CALL_MMODE' [/gitlab-runner/riscv-public/builds/21Uxzs_1/8/riscv-ci/cva6/core/cva6.sv:1146]
ERROR: [Synth 8-660] unable to resolve 'ENV_CALL_SMODE' [/gitlab-runner/riscv-public/builds/21Uxzs_1/8/riscv-ci/cva6/core/cva6.sv:1147]
ERROR: [Synth 8-660] unable to resolve 'ENV_CALL_UMODE' [/gitlab-runner/riscv-public/builds/21Uxzs_1/8/riscv-ci/cva6/core/cva6.sv:1148]
ERROR: [Synth 8-660] unable to resolve 'CVA6DefaultCfg' [/gitlab-runner/riscv-public/builds/21Uxzs_1/8/riscv-ci/cva6/core/cva6.sv:17]
ERROR: [Synth 8-6156] failed synthesizing module 'cva6' [/gitlab-runner/riscv-public/builds/21Uxzs_1/8/riscv-ci/cva6/core/cva6.sv:16]
ERROR: [Synth 8-6156] failed synthesizing module 'ariane' [/gitlab-runner/riscv-public/builds/21Uxzs_1/8/riscv-ci/cva6/corev_apu/src/ariane.sv:16]
ERROR: [Synth 8-6156] failed synthesizing module 'ariane_xilinx' [/gitlab-runner/riscv-public/builds/21Uxzs_1/8/riscv-ci/cva6/corev_apu/fpga/src/ariane_xilinx.sv:14]

zarubaf · 2023-08-02T08:10:44Z

@zarubaf is there any fix for errors raised by the FPGA job?

ERROR: [Synth 8-6038] cannot resolve hierarchical name for the item 'valid' [/gitlab-runner/riscv-public/builds/21Uxzs_1/8/riscv-ci/cva6/core/cva6.sv:1145] ERROR: [Synth 8-660] unable to resolve 'ENV_CALL_MMODE' [/gitlab-runner/riscv-public/builds/21Uxzs_1/8/riscv-ci/cva6/core/cva6.sv:1146] ERROR: [Synth 8-660] unable to resolve 'ENV_CALL_SMODE' [/gitlab-runner/riscv-public/builds/21Uxzs_1/8/riscv-ci/cva6/core/cva6.sv:1147] ERROR: [Synth 8-660] unable to resolve 'ENV_CALL_UMODE' [/gitlab-runner/riscv-public/builds/21Uxzs_1/8/riscv-ci/cva6/core/cva6.sv:1148] ERROR: [Synth 8-660] unable to resolve 'CVA6DefaultCfg' [/gitlab-runner/riscv-public/builds/21Uxzs_1/8/riscv-ci/cva6/core/cva6.sv:17] ERROR: [Synth 8-6156] failed synthesizing module 'cva6' [/gitlab-runner/riscv-public/builds/21Uxzs_1/8/riscv-ci/cva6/core/cva6.sv:16] ERROR: [Synth 8-6156] failed synthesizing module 'ariane' [/gitlab-runner/riscv-public/builds/21Uxzs_1/8/riscv-ci/cva6/corev_apu/src/ariane.sv:16] ERROR: [Synth 8-6156] failed synthesizing module 'ariane_xilinx' [/gitlab-runner/riscv-public/builds/21Uxzs_1/8/riscv-ci/cva6/corev_apu/fpga/src/ariane_xilinx.sv:14]

I think I have changed/fixed this. But the latest regression didn't run fully for some reason.

cathales · 2023-08-02T13:17:03Z

corev_apu/fpga/src/ariane_xilinx.sv

@@ -573,7 +564,7 @@ logic [1:0]    axi_adapter_size;
 assign axi_adapter_size = (riscv::XLEN == 64) ? 2'b11 : 2'b10;

 axi_adapter #(
-    .CVA6Cfg               ( CVA6Cfg                  ),
+    .CVA6Cfg               ( ariane_soc::CVA6SoCCfg   ),


@ASintzoff and I have found that the issue was that rvfi was not supposed to be enabled in FPGA (see deleted line 160).

Below is my suggestion to only overwrite this parameter. It is an unpretty quick fix, but it makes the PR pass the dashboard tests. So I suggest to accept it, to be able to merge this PR, and proceed to better modifications later.

Suggested change

.CVA6Cfg ( ariane_soc::CVA6SoCCfg ),

.CVA6Cfg ('{

NrCommitPorts: ariane_soc::CVA6SoCCfg.NrCommitPorts,

IsRVFI: '0,

AxiAddrWidth: ariane_soc::CVA6SoCCfg.AxiAddrWidth,

AxiDataWidth: ariane_soc::CVA6SoCCfg.AxiDataWidth,

AxiIdWidth: ariane_soc::CVA6SoCCfg.AxiIdWidth,

AxiUserWidth: ariane_soc::CVA6SoCCfg.AxiUserWidth,

RASDepth: ariane_soc::CVA6SoCCfg.RASDepth,

BTBEntries: ariane_soc::CVA6SoCCfg.BTBEntries,

BHTEntries: ariane_soc::CVA6SoCCfg.BHTEntries,

DmBaseAddress: ariane_soc::CVA6SoCCfg.DmBaseAddress,

NrPMPEntries: ariane_soc::CVA6SoCCfg.NrPMPEntries,

NOCType: ariane_soc::CVA6SoCCfg.NOCType,

// idempotent region

NrNonIdempotentRules: ariane_soc::CVA6SoCCfg.NrNonIdempotentRules,

NonIdempotentAddrBase: ariane_soc::CVA6SoCCfg.NonIdempotentAddrBase,

NonIdempotentLength: ariane_soc::CVA6SoCCfg.NonIdempotentLength,

NrExecuteRegionRules: ariane_soc::CVA6SoCCfg.NrExecuteRegionRules,

ExecuteRegionAddrBase: ariane_soc::CVA6SoCCfg.ExecuteRegionAddrBase,

ExecuteRegionLength: ariane_soc::CVA6SoCCfg.ExecuteRegionLength,

// cached region

NrCachedRegionRules: ariane_soc::CVA6SoCCfg.NrCachedRegionRules,

CachedRegionAddrBase: ariane_soc::CVA6SoCCfg.CachedRegionAddrBase,

CachedRegionLength: ariane_soc::CVA6SoCCfg.CachedRegionLength

}),

I think I would prefer to keep rvfi on the FPGA as well, I think it should be synthesisable and it could become useful in the future in case we want to profile CVA6 on the FPGA.

What do you think?

Until now, there is no rvfi on FPGA.

Enabling rvfi on FPGA is revealing another issue due to localparam type rvfi_instr_t = logic; in ariane_xilinx.sv (see error log).

To avoid resource usage for rvfi when not required, it would be preferable to keep it disabled for now.

@cathales will suggest a fix.

zarubaf · 2023-07-27T10:57:13Z

corev_apu/tb/ariane_testharness.sv

-    unsigned'(cva6_config_pkg::CVA6ConfigAxiIdWidth),     // AxiIdWidth
-    unsigned'(cva6_config_pkg::CVA6ConfigDataUserWidth)   // AxiUserWidth
-  },
+  parameter ariane_pkg::cva6_cfg_t CVA6Cfg = ariane_soc::CVA6SoCCfg,


That would create a dependency again from the soc into the main core, memory regions are inherently tied to the SoC which is using the core and I want to keep those as part of the SoC package (if that makes sense). I think we need to live with this duplication here :/

zarubaf · 2023-08-02T13:19:06Z

corev_apu/fpga/src/ariane_xilinx.sv

@@ -720,6 +710,7 @@ ariane #(
    .irq_i        ( irq                 ),
    .ipi_i        ( ipi                 ),
    .time_irq_i   ( timer_irq           ),
+    .rvfi_o       ( /* open */          ),


I don't think there is a harm to enabling it for the FPGA as well, or is there? I would prefer this fix instead of the overwrite.

cathales · 2023-08-03T08:33:19Z

corev_apu/fpga/src/ariane_xilinx.sv

 localparam type rvfi_instr_t = logic;



We have found with @Gchauvon that the issue was this type. Below is a suggestion (perhaps we should reduce repetition in the code later).

Suggested change

localparam type rvfi_instr_t = logic;

localparam type rvfi_instr_t = struct packed {

logic [ariane_pkg::NRET-1:0] valid;

logic [ariane_pkg::NRET*64-1:0] order;

logic [ariane_pkg::NRET*ariane_pkg::ILEN-1:0] insn;

logic [ariane_pkg::NRET-1:0] trap;

logic [ariane_pkg::NRET*riscv::XLEN-1:0] cause;

logic [ariane_pkg::NRET-1:0] halt;

logic [ariane_pkg::NRET-1:0] intr;

logic [ariane_pkg::NRET*2-1:0] mode;

logic [ariane_pkg::NRET*2-1:0] ixl;

logic [ariane_pkg::NRET*5-1:0] rs1_addr;

logic [ariane_pkg::NRET*5-1:0] rs2_addr;

logic [ariane_pkg::NRET*riscv::XLEN-1:0] rs1_rdata;

logic [ariane_pkg::NRET*riscv::XLEN-1:0] rs2_rdata;

logic [ariane_pkg::NRET*5-1:0] rd_addr;

logic [ariane_pkg::NRET*riscv::XLEN-1:0] rd_wdata;

logic [ariane_pkg::NRET*riscv::XLEN-1:0] pc_rdata;

logic [ariane_pkg::NRET*riscv::XLEN-1:0] pc_wdata;

logic [ariane_pkg::NRET*riscv::VLEN-1:0] mem_addr;

logic [ariane_pkg::NRET*riscv::PLEN-1:0] mem_paddr;

logic [ariane_pkg::NRET*(riscv::XLEN/8)-1:0] mem_rmask;

logic [ariane_pkg::NRET*(riscv::XLEN/8)-1:0] mem_wmask;

logic [ariane_pkg::NRET*riscv::XLEN-1:0] mem_rdata;

logic [ariane_pkg::NRET*riscv::XLEN-1:0] mem_wdata;

};

Jbalkind · 2023-09-13T14:42:22Z

Is this PR blocked on something in particular?

cathales · 2023-09-13T14:50:48Z

There was an issue with RVFI synthesis (on FPGA IIRC) but we didn’t know it as RVFI was disabled for synthesis.

This PR enables RVFI so it reveals the issue (that was already there). So the dashboard won’t pass. A patch has been suggested to disable RVFI but it was rejected. Another patch to fix RVFI has been suggested but not accepted (yet?).

Also, as this PR is older than the merge of core-v-verif into cva6, we need it to be rebased to prevent bad things from happening when merging it.

JeanRochCoulon · 2023-09-13T14:55:17Z

This RVFI issue is fixed in the master. A rebase is necessary to integrate all the PRs made since then.
Warning: PR submitted in core-v-verif should be imported in cva6 repository.

zarubaf · 2023-09-13T16:16:55Z

I will try to rebase tomorrow, but likely that all the changes that went in in the meantime created a big mess during the rebase and that this work is lost.

zarubaf · 2023-09-14T10:11:22Z

Okay after half a day of rebasing here it is. Let's see what the CI will say. Can we maybe derive a strategy together on how we manage the amount of different configs we maintain as part of the repository?

github-actions · 2023-09-14T11:11:39Z

❌ failed run, report available here.

JeanRochCoulon · 2023-09-15T07:04:52Z

Agree. The configs to be supported can be listed in the User manual maintained by @jquevremont. Why not discussing it during the next West Shifted meeting? This allows @Jbalkind attendance.

corev_apu/fpga/src/ariane_xilinx.sv

github-actions · 2023-09-26T09:38:56Z

❌ failed run, report available here.

cathales · 2023-09-26T09:45:52Z

Only one red item left in the report! ASIC area: +20kGates

JeanRochCoulon · 2023-09-26T10:17:14Z

The BTB, BHT are present in the PR configuration, which is not the case in native embedded configuration. I think the BHT, BTB, maybe RAS are not well transmitted.

zarubaf · 2023-09-26T11:15:05Z

The BTB, BHT are present in the PR configuration, which is not the case in native embedded configuration. I think the BHT, BTB, maybe RAS are not well transmitted.

Which config is being synthesised? How did you enable/disable the branch predictors before?

cathales · 2023-09-26T11:43:51Z

core/cva6.sv

+    CVA6Cfg.ExceptionAddress,
+    CVA6Cfg.RASDepth,
+    CVA6Cfg.BTBEntries,
+    CVA6Cfg.BHTEntries,


This parameter is not transmitted in CVA6Cfg yet. It is only in the package for now. https://github.com/openhwgroup/cva6/blob/master/core/include/cv32a60x_config_pkg.sv

zarubaf · 2023-09-26T18:03:33Z

core/include/cv32a60x_config_pkg.sv

+      RASDepth:      unsigned'(CVA6ConfigRASDepth),
+      BTBEntries:    unsigned'(CVA6ConfigBTBEntries),
+      BHTEntries:    unsigned'(CVA6ConfigBHTEntries),


@cathales here the parameter is assigned to the struct. I don't think I understand why the predictors are not parameterised correctly.

I think this user config is not the one CVA6Cfg (cva6.sv) refers to.

https://github.com/openhwgroup/cva6/blob/a95d7486d2de1768edd567d3f4daad1cdfb12d17/core/cva6.sv#L18C1-L18C1

parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_default

The user configuration is cva6_config_pkg::cva6_cfg.

Don't we have a synthesis wrapper that sets this to the correct synthesis configuration that we are interested in? Seems dangerous to rely on the default. Do you know where the synthesis wrapper is located?

We set TARGET: .gitlab-ci.yml:322

We make cva6_synth in pd/synth: .gitlab-ci.yml:312

It schedules analysis of files from Flist: pd/synth/Makefile:pre_cva6_synth

This file references a TARGET_CFG variable: core/Flist.cva6:59

Starts cva6_synth.tcl in dc_shell: pd/synth/Makefile:37. It transfers EXPORT_LIST (pd/synth/Makefile:22) to dc_shell (I’m not sure how it is used, I guess it defines Tcl variables from it), with environment variables TARGET and DESIGN_NAME=cva6 (pd/synth/Makefile:11)

Sets TARGET_CFG: pd/synth/cva6_synth.tcl to the TARGET variable from EXPORT_LIST I guess, hence from the environment.

Elaborates DESIGN_NAME: pd/synth/cva6_synth.tcl:30

So I guess the cva6 module from core/cva6.sv:16 is used as the top level, which the synthesis log seem to confirm.

RASDepth, BTBEntries, BHTEntries, DmBaseAddress, NrPMPEntries are now part of CVA6Cfg. This is a breaking change, but it is necessary to make the code more readable and to avoid passing around two parameters. Signed-off-by: Florian Zaruba <[email protected]>

Signed-off-by: Florian Zaruba <[email protected]>

Co-authored-by: Côme <[email protected]>

github-actions · 2023-09-26T19:14:35Z

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core/include/cv32a6_imac_sv0_config_pkg.sv

core/include/cv32a6_imafc_sv32_config_pkg.sv

Co-authored-by: Côme <[email protected]>

github-actions · 2023-09-27T19:43:47Z

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Co-authored-by: Côme <[email protected]>

github-actions · 2023-09-28T07:21:16Z

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JeanRochCoulon · 2023-09-28T09:40:53Z

Thanks @zarubaf The synthesis is not clean, but I propose to fix it after the merge.

zarubaf requested review from jquevremont and JeanRochCoulon as code owners July 26, 2023 11:10

JeanRochCoulon reviewed Jul 26, 2023

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zarubaf force-pushed the zarubaf/fix/merge-parameterization branch 2 times, most recently from 34f24be to f174a6d Compare July 26, 2023 13:07

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zarubaf mentioned this pull request Jul 28, 2023

Adapt for new parameterization openhwgroup/core-v-verif#2090

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This was referenced Aug 22, 2023

Add Variant into CVA6 parameter #1320

Merged

Consolidate top-level CVA6 parameters into struct of parameters #744

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Jbalkind mentioned this pull request Aug 29, 2023

Avoid using System Verilog defines in RTL code #483

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zarubaf force-pushed the zarubaf/fix/merge-parameterization branch from bd6f8c9 to 9927f6b Compare September 14, 2023 10:08

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zarubaf and others added 13 commits September 26, 2023 20:04

Merge CVA6Cfg and ArianeCfg

9347691

RASDepth, BTBEntries, BHTEntries, DmBaseAddress, NrPMPEntries are now part of CVA6Cfg. This is a breaking change, but it is necessary to make the code more readable and to avoid passing around two parameters. Signed-off-by: Florian Zaruba <[email protected]>

Fully deprecate ariane_cfg_t

1e954c7

Signed-off-by: Florian Zaruba <[email protected]>

Use CVA6ConfigRvfiTrace also in ariane_soc_pkg

834f70c

Signed-off-by: Florian Zaruba <[email protected]>

Re-name bus type and include endianess swap for L15

dd50e37

Signed-off-by: Florian Zaruba <[email protected]>

Add an empty rvfi to the FPGA

acdac8d

Signed-off-by: Florian Zaruba <[email protected]>

Clean-up merge problems

82d5645

Signed-off-by: Florian Zaruba <[email protected]>

Remove ArianeCfg from cva6_tb_wrapper

d7080ea

Signed-off-by: Florian Zaruba <[email protected]>

Unify ZiCondExtEn flag

7e077b8

Signed-off-by: Florian Zaruba <[email protected]>

cva6: Fix package path and add ZiCondExtEn parameter

725642c

Signed-off-by: Florian Zaruba <[email protected]>

fpga: Retrieve parameters from ariane_soc package

6eef450

Signed-off-by: Florian Zaruba <[email protected]>

Add NrLoadBufEntries to ariane_xilinx

0f761f9

Signed-off-by: Florian Zaruba <[email protected]>

Update corev_apu/fpga/src/ariane_xilinx.sv

4a5d29c

Co-authored-by: Côme <[email protected]>

ariane_xilinx: Add RVZCB

0c721a4

zarubaf force-pushed the zarubaf/fix/merge-parameterization branch from 532104b to 0c721a4 Compare September 26, 2023 18:13

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Update core/include/cv32a6_imafc_sv32_config_pkg.sv

6a2d537

Co-authored-by: Côme <[email protected]>

Update core/include/cv32a6_imac_sv0_config_pkg.sv

a95d748

Co-authored-by: Côme <[email protected]>

JeanRochCoulon merged commit 93782dd into openhwgroup:master Sep 28, 2023
7 checks passed

-    .CVA6Cfg               ( ariane_soc::CVA6SoCCfg   ),
+    .CVA6Cfg ('{
+        NrCommitPorts: ariane_soc::CVA6SoCCfg.NrCommitPorts,
+        IsRVFI:        '0,
+        AxiAddrWidth:  ariane_soc::CVA6SoCCfg.AxiAddrWidth,
+        AxiDataWidth:  ariane_soc::CVA6SoCCfg.AxiDataWidth,
+        AxiIdWidth:    ariane_soc::CVA6SoCCfg.AxiIdWidth,
+        AxiUserWidth:  ariane_soc::CVA6SoCCfg.AxiUserWidth,
+        RASDepth:      ariane_soc::CVA6SoCCfg.RASDepth,
+        BTBEntries:    ariane_soc::CVA6SoCCfg.BTBEntries,
+        BHTEntries:    ariane_soc::CVA6SoCCfg.BHTEntries,
+        DmBaseAddress: ariane_soc::CVA6SoCCfg.DmBaseAddress,
+        NrPMPEntries:  ariane_soc::CVA6SoCCfg.NrPMPEntries,
+        NOCType:       ariane_soc::CVA6SoCCfg.NOCType,
+        // idempotent region
+        NrNonIdempotentRules:  ariane_soc::CVA6SoCCfg.NrNonIdempotentRules,
+        NonIdempotentAddrBase: ariane_soc::CVA6SoCCfg.NonIdempotentAddrBase,
+        NonIdempotentLength:   ariane_soc::CVA6SoCCfg.NonIdempotentLength,
+        NrExecuteRegionRules:  ariane_soc::CVA6SoCCfg.NrExecuteRegionRules,
+        ExecuteRegionAddrBase: ariane_soc::CVA6SoCCfg.ExecuteRegionAddrBase,
+        ExecuteRegionLength:   ariane_soc::CVA6SoCCfg.ExecuteRegionLength,
+        // cached region
+        NrCachedRegionRules:   ariane_soc::CVA6SoCCfg.NrCachedRegionRules,
+        CachedRegionAddrBase:  ariane_soc::CVA6SoCCfg.CachedRegionAddrBase,
+        CachedRegionLength:    ariane_soc::CVA6SoCCfg.CachedRegionLength
+    }),

-localparam type rvfi_instr_t = logic;
+localparam type rvfi_instr_t = struct packed {
+  logic [ariane_pkg::NRET-1:0]                  valid;
+  logic [ariane_pkg::NRET*64-1:0]               order;
+  logic [ariane_pkg::NRET*ariane_pkg::ILEN-1:0] insn;
+  logic [ariane_pkg::NRET-1:0]                  trap;
+  logic [ariane_pkg::NRET*riscv::XLEN-1:0]      cause;
+  logic [ariane_pkg::NRET-1:0]                  halt;
+  logic [ariane_pkg::NRET-1:0]                  intr;
+  logic [ariane_pkg::NRET*2-1:0]                mode;
+  logic [ariane_pkg::NRET*2-1:0]                ixl;
+  logic [ariane_pkg::NRET*5-1:0]                rs1_addr;
+  logic [ariane_pkg::NRET*5-1:0]                rs2_addr;
+  logic [ariane_pkg::NRET*riscv::XLEN-1:0]      rs1_rdata;
+  logic [ariane_pkg::NRET*riscv::XLEN-1:0]      rs2_rdata;
+  logic [ariane_pkg::NRET*5-1:0]                rd_addr;
+  logic [ariane_pkg::NRET*riscv::XLEN-1:0]      rd_wdata;
+  logic [ariane_pkg::NRET*riscv::XLEN-1:0]      pc_rdata;
+  logic [ariane_pkg::NRET*riscv::XLEN-1:0]      pc_wdata;
+  logic [ariane_pkg::NRET*riscv::VLEN-1:0]      mem_addr;
+  logic [ariane_pkg::NRET*riscv::PLEN-1:0]      mem_paddr;
+  logic [ariane_pkg::NRET*(riscv::XLEN/8)-1:0]  mem_rmask;
+  logic [ariane_pkg::NRET*(riscv::XLEN/8)-1:0]  mem_wmask;
+  logic [ariane_pkg::NRET*riscv::XLEN-1:0]      mem_rdata;
+  logic [ariane_pkg::NRET*riscv::XLEN-1:0]      mem_wdata;
+};

Merge CVA6Cfg and ArianeCfg #1321

Merge CVA6Cfg and ArianeCfg #1321

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zarubaf commented Jul 26, 2023 • edited Loading

How has that been tested?

Jbalkind commented Jul 26, 2023

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Jbalkind commented Sep 13, 2023

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github-actions bot commented Sep 26, 2023

github-actions bot commented Sep 27, 2023

github-actions bot commented Sep 28, 2023

JeanRochCoulon commented Sep 28, 2023

Merge `CVA6Cfg` and `ArianeCfg` #1321

Merge `CVA6Cfg` and `ArianeCfg` #1321

zarubaf commented Jul 26, 2023 •

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JeanRochCoulon commented Sep 13, 2023 •

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