Re-name bus type and include endianess swap for L15

Signed-off-by: Florian Zaruba <[email protected]>
openhwgroup · Jul 26, 2023 · 342589f · 342589f
1 parent f174a6d
commit 342589f
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Showing 6 changed files with 14 additions and 11 deletions.
diff --git a/core/cache_subsystem/cva6_icache.sv b/core/cache_subsystem/cva6_icache.sv
@@ -126,7 +126,7 @@ module cva6_icache import ariane_pkg::*; import wt_cache_pkg::*; #(
   assign cl_index    = vaddr_d[ICACHE_INDEX_WIDTH-1:ICACHE_OFFSET_WIDTH];
 
 
-  if (CVA6Cfg.BusType == ariane_pkg::BUS_TYPE_AXI4_ATOP) begin : gen_axi_offset
+  if (CVA6Cfg.NOCType == ariane_pkg::NOC_TYPE_AXI4_ATOP) begin : gen_axi_offset
     // if we generate a noncacheable access, the word will be at offset 0 or 4 in the cl coming from memory
     assign cl_offset_d = ( dreq_o.ready & dreq_i.req)      ? {dreq_i.vaddr>>2, 2'b0} :
                          ( paddr_is_nc  & mem_data_req_o ) ? cl_offset_q[2]<<2 : // needed since we transfer 32bit over a 64bit AXI bus in this case

diff --git a/core/cache_subsystem/wt_dcache_mem.sv b/core/cache_subsystem/wt_dcache_mem.sv
@@ -255,7 +255,7 @@ module wt_dcache_mem import ariane_pkg::*; import wt_cache_pkg::*; #(
   assign wbuffer_ruser = wbuffer_data_i[wbuffer_hit_idx].user;
   assign wbuffer_be    = (|wbuffer_hit_oh) ? wbuffer_data_i[wbuffer_hit_idx].valid : '0;
 
-  if (CVA6Cfg.BusType == ariane_pkg::BUS_TYPE_AXI4_ATOP) begin : gen_axi_offset
+  if (CVA6Cfg.NOCType == ariane_pkg::NOC_TYPE_AXI4_ATOP) begin : gen_axi_offset
       // In case of an uncached read, return the desired XLEN-bit segment of the most recent AXI read
       assign wr_cl_off     = (wr_cl_nc_i) ? (CVA6Cfg.AxiDataWidth == riscv::XLEN) ? '0 :
                               wr_cl_off_i[AXI_OFFSET_WIDTH-1:riscv::XLEN_ALIGN_BYTES] :

diff --git a/core/cache_subsystem/wt_dcache_missunit.sv b/core/cache_subsystem/wt_dcache_missunit.sv
@@ -254,7 +254,7 @@ module wt_dcache_missunit import ariane_pkg::*; import wt_cache_pkg::*; #(
   end
 
   // note: openpiton returns a full cacheline!
-  if (CVA6Cfg.BusType == ariane_pkg::BUS_TYPE_AXI4_ATOP) begin : gen_axi_rtrn_mux
+  if (CVA6Cfg.NOCType == ariane_pkg::NOC_TYPE_AXI4_ATOP) begin : gen_axi_rtrn_mux
     if (CVA6Cfg.AxiDataWidth > 64) begin
       assign amo_rtrn_mux = mem_rtrn_i.data[amo_req_i.operand_a[$clog2(CVA6Cfg.AxiDataWidth/8)-1:3]*64 +: 64];
     end else begin

diff --git a/core/cache_subsystem/wt_l15_adapter.sv b/core/cache_subsystem/wt_l15_adapter.sv
@@ -132,7 +132,9 @@ l15_rtrn_t rtrn_fifo_data;
 
 
   // openpiton is big endian
-  assign l15_req_o.l15_data = swendian64(dcache_data.data);
+  if (CVA6Cfg.NOCType == ariane_pkg::NOC_TYPE_L15_BIG_ENDIAN) assign l15_req_o.l15_data = swendian64(dcache_data.data);
+  else if (CVA6Cfg.NOCType == ariane_pkg::NOC_TYPE_L15_LITTLE_ENDIAN) assign l15_req_o.l15_data = dcache_data.data;
+  else $fatal(1,"[wt_l15_adapter] Unsupported NOC type");
 
   // arbiter
   rrarbiter #(

diff --git a/core/include/ariane_pkg.sv b/core/include/ariane_pkg.sv
@@ -37,15 +37,16 @@ package ariane_pkg;
     localparam int unsigned ILEN = 32;
     localparam int unsigned NRET = 1;
 
-    /// The bustype is a top-level parameter, hence we need a bit more
+    /// The NoC type is a top-level parameter, hence we need a bit more
     /// information on what protocol those type parameters are supporting.
     /// Currently two values are supported"
     typedef enum {
       /// The "classic" AXI4 protocol.
-      BUS_TYPE_AXI4_ATOP,
+      NOC_TYPE_AXI4_ATOP,
       /// In the OpenPiton setting the WT cache is connected to the L15.
-      BUS_TYPE_L15
-    } bus_type_e;
+      NOC_TYPE_L15_BIG_ENDIAN,
+      NOC_TYPE_L15_LITTLE_ENDIAN
+    } noc_type_e;
 
     localparam NrMaxRules = 16;
 
@@ -74,7 +75,7 @@ package ariane_pkg;
       /// Number of PMP entries.
       int unsigned NrPMPEntries;
       /// Set to the bus type in use.
-      bus_type_e   BusType;
+      noc_type_e   NOCType;
       /// Physical Memory Attributes (PMAs)
       /// Number of non idempotent rules.
       int unsigned                      NrNonIdempotentRules;
@@ -114,7 +115,7 @@ package ariane_pkg;
       BHTEntries:    unsigned'(cva6_config_pkg::CVA6ConfigBHTEntries),
       DmBaseAddress: 64'h0,
       NrPMPEntries:  unsigned'(cva6_config_pkg::CVA6ConfigNrPMPEntries),
-      BusType:       BUS_TYPE_AXI4_ATOP,
+      NOCType:       NOC_TYPE_AXI4_ATOP,
       // idempotent region
       NrNonIdempotentRules:  unsigned'(2),
       NonIdempotentAddrBase: 1024'({64'b0, 64'b0}),

diff --git a/corev_apu/tb/ariane_soc_pkg.sv b/corev_apu/tb/ariane_soc_pkg.sv
@@ -82,7 +82,7 @@ package ariane_soc;
     BHTEntries:    cva6_config_pkg::CVA6ConfigBHTEntries,
     DmBaseAddress: DebugBase,
     NrPMPEntries:  unsigned'(cva6_config_pkg::CVA6ConfigNrPMPEntries),
-    BusType:       ariane_pkg::BUS_TYPE_AXI4_ATOP,
+    NOCType:       ariane_pkg::NOC_TYPE_AXI4_ATOP,
     // idempotent region
     NrNonIdempotentRules:  unsigned'(1),
     NonIdempotentAddrBase: 1024'({64'b0}),