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  • Thales DIS
  • France
  • 11:20 (UTC +01:00)

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@ThalesSiliconSecurity

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Popular repositories Loading

  1. programs programs Public

    Forked from openhwgroup/programs

    Documentation for the OpenHW Group's set of CORE-V RISC-V cores

    JavaScript

  2. cva6 cva6 Public

    Forked from ThalesSiliconSecurity/cva6

    The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

    Assembly

  3. core-v-verif core-v-verif Public

    Forked from openhwgroup/core-v-verif

    Functional verification project for the CORE-V family of RISC-V cores.

    Assembly 1

  4. riscv-dv riscv-dv Public

    Forked from chipsalliance/riscv-dv

    Random instruction generator for RISC-V processor verification

    Python

  5. verible-actions-common verible-actions-common Public

    Forked from chipsalliance/verible-actions-common

  6. verible-formatter-action verible-formatter-action Public

    Forked from chipsalliance/verible-formatter-action

    SystemVerilog