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Merge CVA6Cfg and ArianeCfg #1321

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merged 15 commits into from
Sep 28, 2023
Merged

Merge CVA6Cfg and ArianeCfg #1321

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9347691
Merge `CVA6Cfg` and `ArianeCfg`
zarubaf Jul 26, 2023
1e954c7
Fully deprecate `ariane_cfg_t`
zarubaf Jul 26, 2023
834f70c
Use `CVA6ConfigRvfiTrace` also in `ariane_soc_pkg`
zarubaf Jul 26, 2023
dd50e37
Re-name bus type and include endianess swap for L15
zarubaf Jul 26, 2023
acdac8d
Add an empty rvfi to the FPGA
zarubaf Jul 28, 2023
82d5645
Clean-up merge problems
zarubaf Sep 14, 2023
d7080ea
Remove ArianeCfg from `cva6_tb_wrapper`
zarubaf Sep 19, 2023
7e077b8
Unify `ZiCondExtEn` flag
zarubaf Sep 19, 2023
725642c
cva6: Fix package path and add `ZiCondExtEn` parameter
zarubaf Sep 19, 2023
6eef450
fpga: Retrieve parameters from `ariane_soc` package
zarubaf Sep 19, 2023
0f761f9
Add `NrLoadBufEntries` to ariane_xilinx
zarubaf Sep 26, 2023
4a5d29c
Update corev_apu/fpga/src/ariane_xilinx.sv
zarubaf Sep 26, 2023
0c721a4
ariane_xilinx: Add RVZCB
zarubaf Sep 26, 2023
6a2d537
Update core/include/cv32a6_imafc_sv32_config_pkg.sv
zarubaf Sep 27, 2023
a95d748
Update core/include/cv32a6_imac_sv0_config_pkg.sv
zarubaf Sep 28, 2023
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2 changes: 1 addition & 1 deletion core/alu.sv
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Expand Up @@ -297,7 +297,7 @@ module alu import ariane_pkg::*; #(
default: ; // default case to suppress unique warning
endcase
end
if (CVA6Cfg.RCONDEXT) begin
if (CVA6Cfg.ZiCondExtEn) begin
unique case (fu_data_i.operation)
CZERO_EQZ : result_o = (|fu_data_i.operand_b) ? fu_data_i.operand_a : '0; // move zero to rd if rs2 is equal to zero else rs1
CZERO_NEZ : result_o = (|fu_data_i.operand_b) ? '0 : fu_data_i.operand_a; // move zero to rd if rs2 is nonzero else rs1
Expand Down
5 changes: 2 additions & 3 deletions core/cache_subsystem/cache_ctrl.sv
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Expand Up @@ -19,8 +19,7 @@


module cache_ctrl import ariane_pkg::*; import std_cache_pkg::*; #(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter ariane_cfg_t ArianeCfg = ArianeDefaultConfig // contains cacheable regions
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty
) (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
Expand Down Expand Up @@ -251,7 +250,7 @@ module cache_ctrl import ariane_pkg::*; import std_cache_pkg::*; #(
// -------------------------
// Check for cache-ability
// -------------------------
if (!is_inside_cacheable_regions(ArianeCfg, {{{64-riscv::PLEN}{1'b0}}, tag_o, {DCACHE_INDEX_WIDTH{1'b0}}})) begin
if (!config_pkg::is_inside_cacheable_regions(CVA6Cfg, {{{64-riscv::PLEN}{1'b0}}, tag_o, {DCACHE_INDEX_WIDTH{1'b0}}})) begin
mem_req_d.bypass = 1'b1;
state_d = WAIT_REFILL_GNT;
end
Expand Down
10 changes: 4 additions & 6 deletions core/cache_subsystem/cva6_icache.sv
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Expand Up @@ -28,9 +28,7 @@
module cva6_icache import ariane_pkg::*; import wt_cache_pkg::*; #(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
/// ID to be used for read transactions
parameter logic [MEM_TID_WIDTH-1:0] RdTxId = 0,
/// Contains cacheable regions
parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig
parameter logic [MEM_TID_WIDTH-1:0] RdTxId = 0
) (
input logic clk_i,
input logic rst_ni,
Expand Down Expand Up @@ -118,7 +116,7 @@ module cva6_icache import ariane_pkg::*; import wt_cache_pkg::*; #(
assign cl_tag_d = (areq_i.fetch_valid) ? areq_i.fetch_paddr[ICACHE_TAG_WIDTH+ICACHE_INDEX_WIDTH-1:ICACHE_INDEX_WIDTH] : cl_tag_q;

// noncacheable if request goes to I/O space, or if cache is disabled
assign paddr_is_nc = (~cache_en_q) | (~ariane_pkg::is_inside_cacheable_regions(ArianeCfg, {{{64-riscv::PLEN}{1'b0}}, cl_tag_d, {ICACHE_INDEX_WIDTH{1'b0}}}));
assign paddr_is_nc = (~cache_en_q) | (~config_pkg::is_inside_cacheable_regions(CVA6Cfg, {{{64-riscv::PLEN}{1'b0}}, cl_tag_d, {ICACHE_INDEX_WIDTH{1'b0}}}));

// pass exception through
assign dreq_o.ex = areq_i.fetch_exception;
Expand All @@ -132,7 +130,7 @@ module cva6_icache import ariane_pkg::*; import wt_cache_pkg::*; #(
assign cl_index = vaddr_d[ICACHE_INDEX_WIDTH-1:ICACHE_OFFSET_WIDTH];


if (ArianeCfg.AxiCompliant) begin : gen_axi_offset
if (CVA6Cfg.NOCType == config_pkg::NOC_TYPE_AXI4_ATOP) begin : gen_axi_offset
// if we generate a noncacheable access, the word will be at offset 0 or 4 in the cl coming from memory
assign cl_offset_d = ( dreq_o.ready & dreq_i.req) ? {dreq_i.vaddr>>2, 2'b0} :
( paddr_is_nc & mem_data_req_o ) ? cl_offset_q[2]<<2 : // needed since we transfer 32bit over a 64bit AXI bus in this case
Expand Down Expand Up @@ -166,7 +164,7 @@ end else begin : gen_piton_offset
// main control logic
///////////////////////////////////////////////////////
logic addr_ni;
assign addr_ni = is_inside_nonidempotent_regions(ArianeCfg, areq_i.fetch_paddr);
assign addr_ni = config_pkg::is_inside_nonidempotent_regions(CVA6Cfg, areq_i.fetch_paddr);
always_comb begin : p_fsm
// default assignment
state_d = state_q;
Expand Down
4 changes: 1 addition & 3 deletions core/cache_subsystem/cva6_icache_axi_wrapper.sv
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Expand Up @@ -15,7 +15,6 @@

module cva6_icache_axi_wrapper import ariane_pkg::*; import wt_cache_pkg::*; #(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter ariane_cfg_t ArianeCfg = ArianeDefaultConfig, // contains cacheable regions
parameter type axi_req_t = logic,
parameter type axi_rsp_t = logic
) (
Expand Down Expand Up @@ -99,8 +98,7 @@ module cva6_icache_axi_wrapper import ariane_pkg::*; import wt_cache_pkg::*; #(
cva6_icache #(
// use ID 0 for icache reads
.CVA6Cfg ( CVA6Cfg ),
.RdTxId ( 0 ),
.ArianeCfg ( ArianeCfg )
.RdTxId ( 0 )
) i_cva6_icache (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
Expand Down
3 changes: 0 additions & 3 deletions core/cache_subsystem/std_cache_subsystem.sv
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Expand Up @@ -17,7 +17,6 @@

module std_cache_subsystem import ariane_pkg::*; import std_cache_pkg::*; #(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter ariane_cfg_t ArianeCfg = ArianeDefaultConfig, // contains cacheable regions
parameter int unsigned NumPorts = 4,
parameter type axi_ar_chan_t = logic,
parameter type axi_aw_chan_t = logic,
Expand Down Expand Up @@ -67,7 +66,6 @@ module std_cache_subsystem import ariane_pkg::*; import std_cache_pkg::*; #(

cva6_icache_axi_wrapper #(
.CVA6Cfg ( CVA6Cfg ),
.ArianeCfg ( ArianeCfg ),
.axi_req_t ( axi_req_t ),
.axi_rsp_t ( axi_rsp_t )
) i_cva6_icache_axi_wrapper (
Expand All @@ -92,7 +90,6 @@ module std_cache_subsystem import ariane_pkg::*; import std_cache_pkg::*; #(
// Port 3: Store Unit
std_nbdcache #(
.CVA6Cfg ( CVA6Cfg ),
.ArianeCfg ( ArianeCfg ),
.NumPorts ( NumPorts ),
.axi_req_t ( axi_req_t ),
.axi_rsp_t ( axi_rsp_t )
Expand Down
4 changes: 1 addition & 3 deletions core/cache_subsystem/std_nbdcache.sv
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Expand Up @@ -15,7 +15,6 @@

module std_nbdcache import std_cache_pkg::*; import ariane_pkg::*; #(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter ariane_cfg_t ArianeCfg = ArianeDefaultConfig, // contains cacheable regions
parameter int unsigned NumPorts = 4,
parameter type axi_req_t = logic,
parameter type axi_rsp_t = logic
Expand Down Expand Up @@ -93,8 +92,7 @@ import std_cache_pkg::*;
generate
for (genvar i = 0; i < NumPorts; i++) begin : master_ports
cache_ctrl #(
.CVA6Cfg ( CVA6Cfg ),
.ArianeCfg ( ArianeCfg )
.CVA6Cfg ( CVA6Cfg )
) i_cache_ctrl (
.bypass_i ( ~enable_i ),
.busy_o ( busy [i] ),
Expand Down
8 changes: 2 additions & 6 deletions core/cache_subsystem/wt_cache_subsystem.sv
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Expand Up @@ -21,7 +21,6 @@

module wt_cache_subsystem import ariane_pkg::*; import wt_cache_pkg::*; #(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig, // contains cacheable regions
parameter int unsigned NumPorts = 4,
parameter type noc_req_t = logic,
parameter type noc_resp_t = logic
Expand Down Expand Up @@ -77,8 +76,7 @@ module wt_cache_subsystem import ariane_pkg::*; import wt_cache_pkg::*; #(
cva6_icache #(
// use ID 0 for icache reads
.CVA6Cfg ( CVA6Cfg ),
.RdTxId ( 0 ),
.ArianeCfg ( ArianeCfg )
.RdTxId ( 0 )
) i_cva6_icache (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
Expand All @@ -105,8 +103,7 @@ module wt_cache_subsystem import ariane_pkg::*; import wt_cache_pkg::*; #(
.CVA6Cfg ( CVA6Cfg ),
// use ID 1 for dcache reads and amos. note that the writebuffer
// uses all IDs up to DCACHE_MAX_TX-1 for write transactions.
.RdAmoTxId ( 1 ),
.ArianeCfg ( ArianeCfg )
.RdAmoTxId ( 1 )
) i_wt_dcache (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
Expand Down Expand Up @@ -137,7 +134,6 @@ module wt_cache_subsystem import ariane_pkg::*; import wt_cache_pkg::*; #(
`ifdef PITON_ARIANE
wt_l15_adapter #(
.CVA6Cfg ( CVA6Cfg ),
.SwapEndianess ( ArianeCfg.SwapEndianess )
) i_adapter (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
Expand Down
12 changes: 3 additions & 9 deletions core/cache_subsystem/wt_dcache.sv
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Expand Up @@ -18,9 +18,7 @@ module wt_dcache import ariane_pkg::*; import wt_cache_pkg::*; #(
parameter int unsigned NumPorts = 4, // number of miss ports
// ID to be used for read and AMO transactions.
// note that the write buffer uses all IDs up to DCACHE_MAX_TX-1 for write transactions
parameter logic [CACHE_ID_WIDTH-1:0] RdAmoTxId = 1,
// contains cacheable regions
parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig
parameter logic [CACHE_ID_WIDTH-1:0] RdAmoTxId = 1
) (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
Expand Down Expand Up @@ -113,7 +111,6 @@ module wt_dcache import ariane_pkg::*; import wt_cache_pkg::*; #(

wt_dcache_missunit #(
.CVA6Cfg ( CVA6Cfg ),
.AxiCompliant ( ArianeCfg.AxiCompliant ),
.AmoTxId ( RdAmoTxId ),
.NumPorts ( NumPorts )
) i_wt_dcache_missunit (
Expand Down Expand Up @@ -175,8 +172,7 @@ module wt_dcache import ariane_pkg::*; import wt_cache_pkg::*; #(

wt_dcache_ctrl #(
.CVA6Cfg ( CVA6Cfg ),
.RdTxId ( RdAmoTxId ),
.ArianeCfg ( ArianeCfg )
.RdTxId ( RdAmoTxId )
) i_wt_dcache_ctrl (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
Expand Down Expand Up @@ -220,8 +216,7 @@ module wt_dcache import ariane_pkg::*; import wt_cache_pkg::*; #(
assign rd_prio[NumPorts-1] = 1'b0;

wt_dcache_wbuffer #(
.CVA6Cfg ( CVA6Cfg ),
.ArianeCfg ( ArianeCfg )
.CVA6Cfg ( CVA6Cfg )
) i_wt_dcache_wbuffer (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
Expand Down Expand Up @@ -279,7 +274,6 @@ module wt_dcache import ariane_pkg::*; import wt_cache_pkg::*; #(

wt_dcache_mem #(
.CVA6Cfg ( CVA6Cfg ),
.AxiCompliant ( ArianeCfg.AxiCompliant ),
.NumPorts ( NumPorts )
) i_wt_dcache_mem (
.clk_i ( clk_i ),
Expand Down
5 changes: 2 additions & 3 deletions core/cache_subsystem/wt_dcache_ctrl.sv
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Expand Up @@ -15,8 +15,7 @@

module wt_dcache_ctrl import ariane_pkg::*; import wt_cache_pkg::*; #(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter logic [CACHE_ID_WIDTH-1:0] RdTxId = 1, // ID to use for read transactions
parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig // contains cacheable regions
parameter logic [CACHE_ID_WIDTH-1:0] RdTxId = 1
) (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
Expand Down Expand Up @@ -89,7 +88,7 @@ module wt_dcache_ctrl import ariane_pkg::*; import wt_cache_pkg::*; #(
assign miss_size_o = (miss_nc_o) ? data_size_q : 3'b111;

// noncacheable if request goes to I/O space, or if cache is disabled
assign miss_nc_o = (~cache_en_i) | (~ariane_pkg::is_inside_cacheable_regions(ArianeCfg, {{{64-DCACHE_TAG_WIDTH-DCACHE_INDEX_WIDTH}{1'b0}}, address_tag_q, {DCACHE_INDEX_WIDTH{1'b0}}}));
assign miss_nc_o = (~cache_en_i) | (~config_pkg::is_inside_cacheable_regions(CVA6Cfg, {{{64-DCACHE_TAG_WIDTH-DCACHE_INDEX_WIDTH}{1'b0}}, address_tag_q, {DCACHE_INDEX_WIDTH{1'b0}}}));


assign miss_we_o = '0;
Expand Down
5 changes: 2 additions & 3 deletions core/cache_subsystem/wt_dcache_mem.sv
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Expand Up @@ -28,7 +28,6 @@

module wt_dcache_mem import ariane_pkg::*; import wt_cache_pkg::*; #(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter bit AxiCompliant = 1'b0, // set this to 1 when using in conjunction with AXI bus adapter
parameter int unsigned NumPorts = 3
) (
input logic clk_i,
Expand Down Expand Up @@ -256,12 +255,12 @@ module wt_dcache_mem import ariane_pkg::*; import wt_cache_pkg::*; #(
assign wbuffer_ruser = wbuffer_data_i[wbuffer_hit_idx].user;
assign wbuffer_be = (|wbuffer_hit_oh) ? wbuffer_data_i[wbuffer_hit_idx].valid : '0;

if (AxiCompliant) begin : gen_axi_off
if (CVA6Cfg.NOCType == config_pkg::NOC_TYPE_AXI4_ATOP) begin : gen_axi_offset
// In case of an uncached read, return the desired XLEN-bit segment of the most recent AXI read
assign wr_cl_off = (wr_cl_nc_i) ? (CVA6Cfg.AxiDataWidth == riscv::XLEN) ? '0 :
wr_cl_off_i[AXI_OFFSET_WIDTH-1:riscv::XLEN_ALIGN_BYTES] :
wr_cl_off_i[DCACHE_OFFSET_WIDTH-1:riscv::XLEN_ALIGN_BYTES];
end else begin : gen_piton_off
end else begin : gen_piton_offset
assign wr_cl_off = wr_cl_off_i[DCACHE_OFFSET_WIDTH-1:3];
end

Expand Down
3 changes: 1 addition & 2 deletions core/cache_subsystem/wt_dcache_missunit.sv
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Expand Up @@ -16,7 +16,6 @@

module wt_dcache_missunit import ariane_pkg::*; import wt_cache_pkg::*; #(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter bit AxiCompliant = 1'b0, // set this to 1 when using in conjunction with AXI bus adapter
parameter logic [CACHE_ID_WIDTH-1:0] AmoTxId = 1, // TX id to be used for AMOs
parameter int unsigned NumPorts = 4 // number of miss ports
) (
Expand Down Expand Up @@ -255,7 +254,7 @@ module wt_dcache_missunit import ariane_pkg::*; import wt_cache_pkg::*; #(
end

// note: openpiton returns a full cacheline!
if (AxiCompliant) begin : gen_axi_rtrn_mux
if (CVA6Cfg.NOCType == config_pkg::NOC_TYPE_AXI4_ATOP) begin : gen_axi_rtrn_mux
if (CVA6Cfg.AxiDataWidth > 64) begin
assign amo_rtrn_mux = mem_rtrn_i.data[amo_req_i.operand_a[$clog2(CVA6Cfg.AxiDataWidth/8)-1:3]*64 +: 64];
end else begin
Expand Down
7 changes: 3 additions & 4 deletions core/cache_subsystem/wt_dcache_wbuffer.sv
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Expand Up @@ -50,8 +50,7 @@


module wt_dcache_wbuffer import ariane_pkg::*; import wt_cache_pkg::*; #(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig // contains cacheable regions
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty
) (
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
Expand Down Expand Up @@ -141,10 +140,10 @@ module wt_dcache_wbuffer import ariane_pkg::*; import wt_cache_pkg::*; #(
logic is_nc_miss;
logic is_ni;
assign miss_tag = miss_paddr_o[ariane_pkg::DCACHE_INDEX_WIDTH+:ariane_pkg::DCACHE_TAG_WIDTH];
assign is_nc_miss = !ariane_pkg::is_inside_cacheable_regions(ArianeCfg, {{64-DCACHE_TAG_WIDTH-DCACHE_INDEX_WIDTH{1'b0}}, miss_tag, {DCACHE_INDEX_WIDTH{1'b0}}});
assign is_nc_miss = !config_pkg::is_inside_cacheable_regions(CVA6Cfg, {{64-DCACHE_TAG_WIDTH-DCACHE_INDEX_WIDTH{1'b0}}, miss_tag, {DCACHE_INDEX_WIDTH{1'b0}}});
assign miss_nc_o = !cache_en_i || is_nc_miss;
// Non-idempotent if request goes to NI region
assign is_ni = ariane_pkg::is_inside_nonidempotent_regions(ArianeCfg, {{64-DCACHE_TAG_WIDTH-DCACHE_INDEX_WIDTH{1'b0}}, req_port_i.address_tag, {DCACHE_INDEX_WIDTH{1'b0}}});
assign is_ni = config_pkg::is_inside_nonidempotent_regions(CVA6Cfg, {{64-DCACHE_TAG_WIDTH-DCACHE_INDEX_WIDTH{1'b0}}, req_port_i.address_tag, {DCACHE_INDEX_WIDTH{1'b0}}});

assign miss_we_o = 1'b1;
assign miss_vld_bits_o = '0;
Expand Down
8 changes: 4 additions & 4 deletions core/cache_subsystem/wt_l15_adapter.sv
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Expand Up @@ -50,8 +50,7 @@


module wt_l15_adapter import ariane_pkg::*; import wt_cache_pkg::*; #(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter bit SwapEndianess = 1
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty
) (
input logic clk_i,
input logic rst_ni,
Expand Down Expand Up @@ -133,8 +132,9 @@ l15_rtrn_t rtrn_fifo_data;


// openpiton is big endian
if (SwapEndianess) assign l15_req_o.l15_data = swendian64(dcache_data.data);
else assign l15_req_o.l15_data = dcache_data.data;
if (CVA6Cfg.NOCType == config_pkg::NOC_TYPE_L15_BIG_ENDIAN) assign l15_req_o.l15_data = swendian64(dcache_data.data);
else if (CVA6Cfg.NOCType == config_pkg::NOC_TYPE_L15_LITTLE_ENDIAN) assign l15_req_o.l15_data = dcache_data.data;
else $fatal(1,"[wt_l15_adapter] Unsupported NOC type");

// arbiter
rrarbiter #(
Expand Down
8 changes: 3 additions & 5 deletions core/csr_regfile.sv
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Expand Up @@ -15,9 +15,7 @@

module csr_regfile import ariane_pkg::*; #(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter logic [63:0] DmBaseAddress = 64'h0, // debug module base address
parameter int AsidWidth = 1,
parameter int unsigned NrPMPEntries = 8,
parameter int unsigned MHPMCounterNum = 6
) (
input logic clk_i, // Clock
Expand Down Expand Up @@ -909,7 +907,7 @@ module csr_regfile import ariane_pkg::*; #(
mstatus_d.sd = (mstatus_q.xs == riscv::Dirty) | (mstatus_q.fs == riscv::Dirty);

// reserve PMPCFG bits 5 and 6 (hardwire to 0)
for (int i = 0; i < NrPMPEntries; i++) pmpcfg_d[i].reserved = 2'b0;
for (int i = 0; i < CVA6Cfg.NrPMPEntries; i++) pmpcfg_d[i].reserved = 2'b0;

// write the floating point status register
if (CVA6Cfg.FpPresent && csr_write_fflags_i) begin
Expand Down Expand Up @@ -1269,7 +1267,7 @@ module csr_regfile import ariane_pkg::*; #(

// if we are in debug mode jump to a specific address
if (debug_mode_q) begin
trap_vector_base_o = DmBaseAddress[riscv::VLEN-1:0] + CVA6Cfg.ExceptionAddress[riscv::VLEN-1:0];
trap_vector_base_o = CVA6Cfg.DmBaseAddress[riscv::VLEN-1:0] + CVA6Cfg.ExceptionAddress[riscv::VLEN-1:0];
end

// check if we are in vectored mode, if yes then do BASE + 4 * cause we
Expand Down Expand Up @@ -1442,7 +1440,7 @@ module csr_regfile import ariane_pkg::*; #(
wfi_q <= wfi_d;
// pmp
for(int i = 0; i < 16; i++) begin
if(i < NrPMPEntries) begin
if(i < CVA6Cfg.NrPMPEntries) begin
// We only support >=8-byte granularity, NA4 is disabled
if(pmpcfg_d[i].addr_mode != riscv::NA4 && !(pmpcfg_d[i].access_type.r == '0 && pmpcfg_d[i].access_type.w == '1)) begin
pmpcfg_q[i] <= pmpcfg_d[i];
Expand Down
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