New: io / param describes internal parameters, not exposed in top level

New: prints errors details after a testcase status Change: SYNC_RD_WR parameter is driven from processing to memfy now Chnage: Remove useless AXI_REORDER_CPL parameter on memfy
dpretet · Sep 6, 2023 · 20b39fa · 20b39fa
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diff --git a/doc/ios_params.md b/doc/ios_params.md
@@ -145,33 +145,33 @@ All parameters listed in [core](#core) section apply here
 
 - aresetn
     - the main asynchronous active low reset
-    - input
+    - input, 1 bit
     - don't use it if already using srst
 
 - srst
     - the main synchronous active high reset
-    - input
+    - input, 1 bit
     - don't use it if already using aresetn
 
 - ext_irq
     - external interrupt, from any hardware source
-    - input
+    - input, 1 bit
 
 - sw_irq
     - software interrupt, from any other hart or PLIC controller
-    - input
+    - input, 1 bit
 
 - timer_irq
     - timer interrupt, from CLINT controller
-    - input
+    - input, 1 bit
 
 - status
     - debug bus
     - output
 
 - dbg_regs
     - all the ISA registers
-    - output
+    - output, 32 * XLEN bits
 
 - imem_*
     - AXI4-lite instruction bus (read channels only)
@@ -180,3 +180,29 @@ All parameters listed in [core](#core) section apply here
 - dmem_*
     - AXI4-lite data bus
     - input/output
+
+
+# Hidden Parameters
+
+List some parameters not present on top level but which could be tuned into the hart or the platform
+
+## dCache
+
+FAST_FWD_CPL:
+- Bypass if possible the OoO output RAM stage. Imply the completion path
+  will be combinatorial but reduce the latency, increase the bandwidth. Avoid
+- Default: 1
+
+NO_CPL_BACKPRESSURE (block_fetcher instance):
+- Don't manage read data channel back-pressure to have better bandwidth
+- Default: 1
+
+AXI_ID_FIXED:
+- AXI ID issued on slave interface is fixed, save some logic by not using it and use only `AXI_ID_MASK`
+- Default: 1
+
+## Memfy
+
+SYNC_RD_WR
+- Insert a pipeline on Rd write path to close timing easier.
+- Default: 0
diff --git a/doc/project_mgt_hw.md b/doc/project_mgt_hw.md
@@ -1,7 +1,5 @@
 # DOING
 
-- [ ] Revoir tous les paramètres de chaque instance et les documenter
-- [ ] Review readme files
 - [ ] Rework logging by using SVLogger everywhere
 - [ ] Revoir la RAM AXI pour les temps de réponses write compliance et speed
 
@@ -173,7 +171,11 @@ Hardware Tests
 
 # DONE
 
-- [X] Print des tests qui ne marchent pas, un par un, dans le bash
+- [X] v1.5.1: maintenance
+    - [X] Print des tests qui ne marchent pas, un par un, dans le bash
+    - [X] Join errors after a test status
+    - [X] Review readme files
+    - [X] Revoir tous les paramètres de chaque instance et les documenter
 - [X] v1.5.0: Mesure et amélioration des performances
     - [X] Print et save des registres CSRs pour chaque test, garde la trace des performances dans Git
     - [X] IP point de mesure des différents bus en bandwidth

diff --git a/rtl/friscv_memfy.sv b/rtl/friscv_memfy.sv
@@ -51,8 +51,6 @@ module friscv_memfy
         parameter AXI_DATA_W        = XLEN,
         // ID used to identify the dta abus in the infrastructure
         parameter AXI_ID_MASK       = 'h20,
-        // Reorder read completion for Memfy
-        parameter AXI_REORDER_CPL = 0,
         // Maximum outstanding request supported
         parameter MAX_OR = 8,
         // Add pipeline on Rd write stage

diff --git a/rtl/friscv_processing.sv b/rtl/friscv_processing.sv
@@ -33,8 +33,8 @@ module friscv_processing
         parameter INST_BUS_PIPELINE = 0,
         // Number of outstanding requests used by the LOAD/STORE unit
         parameter DATA_OSTDREQ_NUM  = 8,
-        // Reorder read completion internally in Memfy, not in dCache
-        parameter AXI_REORDER_CPL = 0,
+        // Add pipeline on Rd write stage
+        parameter SYNC_RD_WR = 0,
         // IO regions for direct read/write access
         parameter IO_MAP_NB = 1,
         // IO address ranges, organized by memory region as END-ADDR_START-ADDR:
@@ -312,7 +312,7 @@ module friscv_processing
         .AXI_ID_W          (AXI_ID_W),
         .AXI_DATA_W        (AXI_DATA_W),
         .AXI_ID_MASK       (AXI_ID_MASK),
-        .AXI_REORDER_CPL   (AXI_REORDER_CPL),
+        .SYNC_RD_WR        (SYNC_RD_WR),
         .IO_MAP_NB         (IO_MAP_NB),
         .IO_MAP            (IO_MAP)
     )

diff --git a/rtl/friscv_rv32i_core.sv b/rtl/friscv_rv32i_core.sv
@@ -588,7 +588,6 @@ module friscv_rv32i_core
         .AXI_ID_W          (AXI_ID_W),
         .AXI_DATA_W        (XLEN),
         .AXI_ID_MASK       (AXI_DMEM_MASK),
-        .AXI_REORDER_CPL   (0),
         .NB_UNIT           (NB_ALU_UNIT),
         .MAX_UNIT          (MAX_ALU_UNIT),
         .DATA_OSTDREQ_NUM  (DATA_OSTDREQ_NUM),

diff --git a/test/common/functions.sh b/test/common/functions.sh
@@ -157,9 +157,11 @@ get_defines() {
 gather_result() {
 
     ec=$(grep -c "ERROR:" tc.log)
+    msg=$(grep -ni "ERROR:" tc.log)
 
     if [ "$2" -eq 1 ] || [ "$ec" != 0 ]; then
         ts_res="${ts_res} - $1:\t❌\n"
+        ts_res="${ts_res}$msg\n"
     else
         ts_res="${ts_res} - $1:\t✅\n"
     fi