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Change: Plan EmbeddedSwift Support FRISCV #282: Commit 0bf8af2 pushed by dpretet
October 8, 2024 19:01 44m 31s amo
amo
October 8, 2024 19:01 44m 31s
Change: Plan EmbeddedSwift Support FRISCV #281: Commit 2a0676b pushed by dpretet
October 8, 2024 19:00 40m 8s amo
amo
October 8, 2024 19:00 40m 8s
Add git attrubutes to force verilog files detection in github for lin… FRISCV #280: Commit 5bf6d1d pushed by dpretet
October 8, 2024 18:59 22m 37s master
master
October 8, 2024 18:59 22m 37s
Change: Plan EmbeddedSwift Support FRISCV #279: Commit 4212ba2 pushed by dpretet
June 25, 2024 17:45 21m 28s amo
amo
June 25, 2024 17:45 21m 28s
Document atomic operation support FRISCV #278: Commit 985562a pushed by dpretet
April 25, 2024 19:21 17m 56s amo
amo
April 25, 2024 19:21 17m 56s
New: Add Quartus project FRISCV #277: Commit 00b45b0 pushed by dpretet
February 12, 2024 18:33 1h 6m 45s syn_fpga
syn_fpga
February 12, 2024 18:33 1h 6m 45s
Change: syntax update to pass Quartus synthesis FRISCV #276: Commit ddf3ede pushed by dpretet
February 12, 2024 18:32 44m 33s syn_fpga
syn_fpga
February 12, 2024 18:32 44m 33s
Document atomic operation support FRISCV #275: Commit c15e6e9 pushed by dpretet
January 29, 2024 20:11 35m 40s amo
amo
January 29, 2024 20:11 35m 40s
Start atomic operation support FRISCV #274: Commit e3cce76 pushed by dpretet
December 23, 2023 14:25 30m 30s amo
amo
December 23, 2023 14:25 30m 30s
Start atomic operation support FRISCV #273: Commit fa19e4e pushed by dpretet
December 20, 2023 21:08 32m 34s amo
amo
December 20, 2023 21:08 32m 34s
Update README.md FRISCV #272: Commit 5245260 pushed by dpretet
December 12, 2023 14:14 46m 36s master
master
December 12, 2023 14:14 46m 36s
Fix: yosys flow missed source file after parameter defaults' FRISCV #271: Commit 8f0428b pushed by dpretet
December 11, 2023 18:34 1h 14m 2s v1.6.1
v1.6.1
December 11, 2023 18:34 1h 14m 2s
Fix: yosys flow missed source file after parameter defaults' FRISCV #270: Commit 8f0428b pushed by dpretet
December 11, 2023 18:05 43m 12s master
master
December 11, 2023 18:05 43m 12s
Update README with area numbers FRISCV #269: Commit fda5b2a pushed by dpretet
December 11, 2023 17:04 47m 45s master
master
December 11, 2023 17:04 47m 45s
Rework synthesis flow FRISCV #268: Commit 7425350 pushed by dpretet
December 10, 2023 19:48 39m 3s master
master
December 10, 2023 19:48 39m 3s
Clean-up computation and update coremark README FRISCV #267: Commit e076494 pushed by dpretet
December 9, 2023 20:51 31m 52s master
master
December 9, 2023 20:51 31m 52s
Port coremark to FRISCV FRISCV #266: Commit 1b356f0 pushed by dpretet
December 9, 2023 13:05 40m 31s master
master
December 9, 2023 13:05 40m 31s
Porting coremark to FRISCV FRISCV #265: Commit 269524b pushed by dpretet
November 30, 2023 20:04 45m 56s master
master
November 30, 2023 20:04 45m 56s
update docs FRISCV #264: Commit 8c878e7 pushed by dpretet
November 27, 2023 18:13 1h 23m 19s v1.6.0
v1.6.0
November 27, 2023 18:13 1h 23m 19s
update docs FRISCV #263: Commit 8c878e7 pushed by dpretet
November 27, 2023 18:12 39m 15s master
master
November 27, 2023 18:12 39m 15s
update docs FRISCV #262: Commit 8c878e7 pushed by dpretet
November 25, 2023 20:26 1m 21s privilege
privilege
November 25, 2023 20:26 1m 21s
New: Add MCOUNTEREN checks FRISCV #261: Commit 02465d4 pushed by dpretet
November 25, 2023 20:15 30m 57s privilege
privilege
November 25, 2023 20:15 30m 57s
Reindent code by removing tabs FRISCV #260: Commit d86cceb pushed by dpretet
November 22, 2023 20:06 31m 16s privilege
privilege
November 22, 2023 20:06 31m 16s
Change: update REPL app to use config file FRISCV #259: Commit 9ef343f pushed by dpretet
November 21, 2023 19:49 45m 43s privilege
privilege
November 21, 2023 19:49 45m 43s
New: Drive aprot[0] based on current priviledge mode FRISCV #258: Commit 8f3bdc3 pushed by dpretet
November 21, 2023 19:26 30m 25s privilege
privilege
November 21, 2023 19:26 30m 25s