Change: Update README files

New: add wba test updates from memfy_opt branch

test/apps/README.md

@@ -1,11 +1,11 @@
-# Apps Tetsuite
+# Apps Testsuite
 
 ## Overview
 
 This testsuite is composed by several applications, stressing out C toolchain and
 benchmarking the core.
 
-The testbench provides onl;y "platform" support (CPU + AXI4 interconnect). The application
+The testbench provides only "platform" support (CPU + AXI4 interconnect). The applications
 are interactive and require user inputs.
 
 To execute the flow:
@@ -14,11 +14,9 @@ To execute the flow:
 ./run.sh --tc tests/repl.v
 ```
 
-For the moment only a REPL aaplication is available and under desgn.
-
-All the testcases rely on [SVUT](https://github.com/dpretet/svut) and use
+All the testcases rely on [SVUT](https://github.com/dpretet/svut) and
 [Icarus Verilog](http://iverilog.icarus.com) or [Verilator](https://github.com/verilator).
 
 [Common](tests/common) folder contains a Makefile and a linker setup shared between
 all the testcases and symlinked into each test folder. A C runtime (crt0.S) is also provided
-to applications to boot the processor, initialize the stack and jump to the main.
+to boot the processor, initialize the stack and jump to the main.

test/c_testsuite/README.md

@@ -1,25 +1,26 @@
-# C Tetsuite
+# C Testsuite
 
 ## Overview
 
 This testsuite is composed by several applications, stressing out C toolchain and
-benchmarking the core.
+verifying the core. The testsuite is made of various C code, verifying the basics
+of C lang and its support with a hart.
 
 The testbench provides two configurations:
 
-- core: the hart is connected upon an AXI4-lite dual port RAM model, the instruction
-  bus on one port, the data bus on the other
-- platform: the core is connected upon an AXI4 crossbar with some peripherals
-  (GPIOs, UART, CLINT) and share the same master interface to the AXI4-lite RAM molde
+- `core`: the hart is connected upon an AXI4-lite dual port RAM model, the instruction
+  bus on one port, the data bus on the other. Nothing else than a hart.
+- `platform`: the core is connected upon an AXI4 crossbar with some peripherals
+  (GPIOs, UART, CLINT) and share the same master interface to the AXI4-lite RAM model
 
 To execute the flow:
 
 ```bash
-./run.sh --tb "CORE" // to run the core only simulation
-./run.sh --tb "PLATFORM" // to run the platform, the core + the peripherals
+./run.sh --tb "core"     // to run the core-only simulation
+./run.sh --tb "platform" // to run the platform, the core + the peripherals
 ```
 
-This will make all programs in tests\* folders, copy the RAM content generated,
+This will make all programs in tests/* folders, copy the RAM content generated,
 convert it to Verilog format then execute SVUT to run the testbench on each
 testcase.
 
@@ -29,7 +30,7 @@ For more information about the bash front-end flow:
 ./run.sh -h
 ```
 
-All the testcases rely on [SVUT](https://github.com/dpretet/svut) and use
+All the testcases rely on [SVUT](https://github.com/dpretet/svut) and
 [Icarus Verilog](http://iverilog.icarus.com) or [Verilator](https://github.com/verilator).
 
 [Common](tests/common) folder contains a Makefile and a linker setup shared between

test/common/functions.sh

@@ -157,11 +157,11 @@ get_defines() {
 gather_result() {
 
     ec=$(grep -c "ERROR:" tc.log)
-    
+
     if [ "$2" -eq 1 ] || [ "$ec" != 0 ]; then
-        ts_res="${ts_res}$1: ❌\n"
+        ts_res="${ts_res} - $1:\t❌\n"
     else
-        ts_res="${ts_res}$1: ✅\n"
+        ts_res="${ts_res} - $1:\t✅\n"
     fi
 }
 #------------------------------------------------------------------------------

test/riscv-tests/README.md

@@ -1,18 +1,21 @@
 # RISCV-Tests
 
-Official compliance testsuite from [RISCV](https://github.com/riscv/riscv-tests/)
+Official compliance testsuite from [RISCV test github](https://github.com/riscv/riscv-tests/).
 
 To execute the flow:
 
 ```bash
 ./run.sh --simulator icarus
+./run.sh --simulator verilator
+./run.sh --tb platform
+./run.sh --tb core
 ```
 
-This will make all programs in tests\* folders, copy the RAM content generated,
+This will make all programs in tests/* folders, copy the RAM content generated,
 convert it to Verilog format then execute SVUT to run the testbench on each
 testcase.
 
-All the testcases rely on [SVUT](https://github.com/dpretet/svut) and use
+All the testcases rely on [SVUT](https://github.com/dpretet/svut) and
 [Icarus Verilog](http://iverilog.icarus.com) or [Verilator](https://github.com/verilator).
 
 [Common](../common) folder contains a Makefile and a linker setup shared between

test/wba_testsuite/README.md

@@ -4,29 +4,26 @@ WBA testsuite is an example of integration of the processor core in a complete e
 
 The testbench provides two configurations:
 
-- core: the hart is connected upon an AXI4-lite dual port RAM model, the instruction
-  bus on one port, the data bus on the other
-- platform: the core is connected upon an AXI4 crossbar with some peripherals
+- `core`: the hart is connected upon an AXI4-lite dual port RAM model, the instruction
+  bus on one port, the data bus on the other. Hart-only configuration.
+- `platform`: the core is connected upon an AXI4 crossbar with some peripherals
   (GPIOs, UART, CLINT) and share the same master interface to the AXI4-lite RAM molde
 
-For both setup, the test vectors are created from ASM programs, built and then
-converted into files to initialize the RAMs.
-
 The intent of this flow is to create programs to stress the IP's core
-with a white-box strategy.
+with a white-box strategy, very driven by the architecture.
 
 To execute the flow:
 
 ```bash
-./run.sh --tb "CORE" // to run the core only simulation
-./run.sh --tb "PLATFORM" // to run the platform, the core + the peripherals
+./run.sh --tb "core"     // to run the core-only simulation
+./run.sh --tb "platform" // to run the platform, the core + the peripherals
 ```
 
-This will make all programs in tests\* folders, copy the RAM content generated,
+This will make all programs in tests/* folders, copy the RAM content generated,
 convert it to Verilog format then execute SVUT to run the testbench on each
 testcase.
 
-All the testcases rely on [SVUT](https://github.com/dpretet/svut) and use
+All the testcases rely on [SVUT](https://github.com/dpretet/svut) and
 [Icarus Verilog](http://iverilog.icarus.com) or [Verilator](https://github.com/verilator).
 
 For more information about the bash front-end flow:
@@ -82,10 +79,18 @@ to failure in control unit.
 Stresses out outstanding requests management in Memfy module when issuing
 multiple read or write requests.
 
-# Test 7: RDCYCLE/RDTIME and RDINSTRET
+## Test 7: RDCYCLE/RDTIME and RDINSTRET
 
 Checks instret, cycle and time are incremented accordingly the spec
 
-# Test 8: WFI
+## Test 8: WFI
 
 Setup interrupt and checks the core manages EIRQ correctly.
+
+## Test 9: M extension
+
+Check multiply /division extension
+
+## Test 10: load / store collision
+
+Stresses out read / write with memfy and check collisions don't occur

test/wba_testsuite/tests/Makefile

@@ -89,7 +89,6 @@ all: $(tests_dump)
 clean:
 	rm -rf $(junk)
 	rm -fr *.elf
-	rm -fr *.v
 	rm -fr *.dump
 	rm -fr *.gtkw
 	rm -fr *.vcd

test/wba_testsuite/tests/rv32ui-p-test10.v

@@ -0,0 +1,59 @@
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