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Attempt to fix SOF upgrade #69547

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@lyakh lyakh commented Feb 28, 2024

With these changes SOF now can be made to pass CI tests again thesofproject/sof#8732 Please comment and advise how to merge these fixes

@lyakh lyakh requested a review from nashif February 28, 2024 08:17
@nordicjm nordicjm added hwmv2-likely-conflict DNM until collab-hwmv2 has been merged DNM This PR should not be merged (Do Not Merge) labels Feb 28, 2024
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lyakh commented Feb 28, 2024

The first of these commits has also been submitted separately as #69480

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Needs converting to hwmv2

@nordicjm nordicjm removed hwmv2-likely-conflict DNM until collab-hwmv2 has been merged DNM This PR should not be merged (Do Not Merge) labels Mar 4, 2024
kv2019i and others added 9 commits March 4, 2024 15:47
The GEN bit status cannot be immediately read back, so
modify DGCS in one write.

Signed-off-by: Kai Vehmanen <[email protected]>
This function should return true only if DGCS_GEN bit is set.
Having only DGCS_FIFORDY set is not sufficient to consider
the channel to be enabled.

Signed-off-by: Kai Vehmanen <[email protected]>
Setting the Power Active bit to the off state before powering up the core
requires a minimum delay

Signed-off-by: Adrian Bonislawski <[email protected]>
Clearing the LL DONE bit tells the DMAC that this LLI descriptor can
be executed again to initiate another transfer. This should always be
done prior to START but not during STOP.

STOP needs all the LLI descriptors DONE to be set so that any LLI load
will stop the DMA state machine.

Signed-off-by: Liam Girdwood <[email protected]>
Currently channel start unmasks several IRQ sources depending on DMA
configuration but DMA stop does not remask them. Fix this.

Also clear and unhandled or dont care IRQ at channel stop.

Signed-off-by: Liam Girdwood <[email protected]>
On Intel ADSP platforms, addition "isync" is needed in interrupt
vector to synchronize icache when interrupt is received when core
is in deeper sleep state.

Signed-off-by: Kai Vehmanen <[email protected]>
On Intel ADSP we choose to only serve the timer interrupt on the
primary core.

Signed-off-by: Guennadi Liakhovetski <[email protected]>
power_down() locks the cache line, containing the address, passed to
the function in its second argument. However, current builds cause an
"alloca" DSP exception when trying to lock that cache line. Aligning
that variable on a cache-line size border fixes the problem.

Signed-off-by: Guennadi Liakhovetski <[email protected]>
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4 participants