Attempt to fix SOF upgrade

arch/xtensa/include/xtensa_asm2_s.h

@@ -594,6 +594,11 @@ _Level\LVL\()Vector:
 	s32i a2, a1, ___xtensa_irq_bsa_t_a2_OFFSET
 	s32i a3, a1, ___xtensa_irq_bsa_t_a3_OFFSET
 
+#ifdef CONFIG_SOC_FAMILY_INTEL_ADSP
+	/* Needed when waking from low-power waiti state */
+	isync
+#endif
+
 	/* Level "1" is the exception handler, which uses a different
 	 * calling convention.  No special register holds the
 	 * interrupted PS, instead we just assume that the CPU has

drivers/dma/dma_dw_common.c

@@ -493,6 +493,11 @@ int dw_dma_start(const struct device *dev, uint32_t channel)
 	dw_write(dev_cfg->base, DW_LLP(channel), llp);
 	LOG_DBG("%s: ctrl_lo %x, masked ctrl_lo %x, LLP %x", dev->name,
 		lli->ctrl_lo, masked_ctrl_lo, dw_read(dev_cfg->base, DW_LLP(channel)));
+
+	/* clear DONE bit for all LLI descriptors */
+	for (int i = 0; i < chan_data->lli_count; i++) {
+		chan_data->lli[i].ctrl_hi &= ~DW_CTLH_DONE(1);
+	}
 #endif /* CONFIG_DMA_DW_HW_LLI */
 
 	/* channel needs to start from scratch, so write SAR and DAR */
@@ -574,8 +579,11 @@ int dw_dma_stop(const struct device *dev, uint32_t channel)
 	}
 
 #ifdef CONFIG_DMA_DW_HW_LLI
-	struct dw_lli *lli = chan_data->lli;
-	int i;
+	/* set DONE for all LLI - make sure any LL reload during STOP
+	 * will be DONE and stop further DMA state machine actions */
+	for (int i = 0; i < chan_data->lli_count; i++) {
+		chan_data->lli[i].ctrl_hi |= DW_CTLH_DONE(1);
+	}
 #endif
 
 	LOG_INF("%s: channel %d stop", dev->name, channel);
@@ -618,12 +626,21 @@ int dw_dma_stop(const struct device *dev, uint32_t channel)
 		return -ETIMEDOUT;
 	}
 
-#if CONFIG_DMA_DW_HW_LLI
-	for (i = 0; i < chan_data->lli_count; i++) {
-		lli->ctrl_hi &= ~DW_CTLH_DONE(1);
-		lli++;
-	}
-#endif
+	/* mask any unmasked IRQs after channel is stopped */
+	dw_write(dev_cfg->base, DW_MASK_ERR, DW_CHAN_MASK(channel));
+	dw_write(dev_cfg->base, DW_MASK_TFR, DW_CHAN_MASK(channel));
+	dw_write(dev_cfg->base, DW_MASK_BLOCK, DW_CHAN_MASK(channel));
+
+	/* clear any pending IRQs - some configuration may not
+	 * assign any handlers or care, but new transfers need to start
+	 * with a clean slate.
+	 */
+	dw_write(dev_cfg->base, DW_CLEAR_TFR, 0x1 << channel);
+	dw_write(dev_cfg->base, DW_CLEAR_BLOCK, 0x1 << channel);
+	dw_write(dev_cfg->base, DW_CLEAR_SRC_TRAN, 0x1 << channel);
+	dw_write(dev_cfg->base, DW_CLEAR_DST_TRAN, 0x1 << channel);
+	dw_write(dev_cfg->base, DW_CLEAR_ERR, 0x1 << channel);
+
 	chan_data->state = DW_DMA_IDLE;
 	ret = pm_device_runtime_put(dev);
 out:

drivers/timer/intel_adsp_timer.c

@@ -210,7 +210,6 @@ static void irq_init(void)
 
 void smp_timer_init(void)
 {
-	irq_init();
 }
 
 /* Runs on core 0 only */

soc/xtensa/intel_adsp/ace/multiprocessing.c

@@ -159,6 +159,7 @@ void soc_start_core(int cpu_num)
 	 * core will not power on properly when doing transition D0->D3->D0.
 	 */
 	DSPCS.capctl[cpu_num].ctl &= ~DSPCS_CTL_SPA;
+	k_busy_wait(5 * HW_STATE_CHECK_DELAY);
 
 	/* Checking current power status of the core. */
 	if (!WAIT_FOR((DSPCS.capctl[cpu_num].ctl & DSPCS_CTL_CPA) != DSPCS_CTL_CPA,
@@ -167,6 +168,7 @@ void soc_start_core(int cpu_num)
 	}
 
 	DSPCS.capctl[cpu_num].ctl |= DSPCS_CTL_SPA;
+	k_busy_wait(5 * HW_STATE_CHECK_DELAY);
 
 	/* Waiting for power up */
 	while (((DSPCS.capctl[cpu_num].ctl & DSPCS_CTL_CPA) != DSPCS_CTL_CPA) &&

soc/xtensa/intel_adsp/ace/power.c

@@ -303,7 +303,7 @@ void pm_state_set(enum pm_state state, uint8_t substate_id)
 					(void *)rom_entry;
 			sys_cache_data_flush_range(imr_layout, sizeof(*imr_layout));
 #endif /* CONFIG_ADSP_IMR_CONTEXT_SAVE */
-			uint32_t hpsram_mask = 0;
+			uint32_t hpsram_mask __aligned(64) = 0;
 #ifdef CONFIG_ADSP_POWER_DOWN_HPSRAM
 			/* turn off all HPSRAM banks - get a full bitmap */
 			uint32_t ebb_banks = ace_hpsram_get_bank_count();

soc/xtensa/intel_adsp/common/include/intel_adsp_hda.h

@@ -213,11 +213,13 @@ static inline uint32_t intel_adsp_hda_get_buffer_size(uint32_t base,
 static inline void intel_adsp_hda_enable(uint32_t base, uint32_t regblock_size,
 					 uint32_t sid, bool set_fifordy)
 {
-	*DGCS(base, regblock_size, sid) |= DGCS_GEN;
+	uint32_t enable = DGCS_GEN;
 
 	if (set_fifordy) {
-		*DGCS(base, regblock_size, sid) |= DGCS_FIFORDY;
+		enable |= DGCS_FIFORDY;
 	}
+
+	*DGCS(base, regblock_size, sid) |= enable;
 }
 
 /**
@@ -241,7 +243,7 @@ static inline void intel_adsp_hda_disable(uint32_t base, uint32_t regblock_size,
  */
 static inline bool intel_adsp_hda_is_enabled(uint32_t base, uint32_t regblock_size, uint32_t sid)
 {
-	return *DGCS(base, regblock_size, sid) & (DGCS_GEN | DGCS_FIFORDY);
+	return *DGCS(base, regblock_size, sid) & DGCS_GEN;
 }
 
 /**

subsys/pm/pm.c

@@ -22,6 +22,9 @@
 #include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(pm, CONFIG_PM_LOG_LEVEL);
 
+#define CURRENT_CPU \
+	(COND_CODE_1(CONFIG_SMP, (arch_curr_cpu()->id), (_current_cpu->id)))
+
 static ATOMIC_DEFINE(z_post_ops_required, CONFIG_MP_MAX_NUM_CPUS);
 static sys_slist_t pm_notifiers = SYS_SLIST_STATIC_INIT(&pm_notifiers);
 
@@ -130,7 +133,7 @@ static inline void pm_state_notify(bool entering_state)
 
 void pm_system_resume(void)
 {
-	uint8_t id = _current_cpu->id;
+	uint8_t id = CURRENT_CPU;
 
 	/*
 	 * This notification is called from the ISR of the event
@@ -168,7 +171,7 @@ bool pm_state_force(uint8_t cpu, const struct pm_state_info *info)
 
 bool pm_system_suspend(int32_t ticks)
 {
-	uint8_t id = _current_cpu->id;
+	uint8_t id = CURRENT_CPU;
 	k_spinlock_key_t key;
 
 	SYS_PORT_TRACING_FUNC_ENTER(pm, system_suspend, ticks);