Release riscv-isa-release-ec3b886-2024-11-07

This release was created by: wmat
Release of RISC-V ISA, built from commit ec3b886, is now available.

What's Changed

• Minor style fix for packh description by @Peter-Herrmann in #1716

Full Changelog: riscv-isa-release-152ef53-2024-11-06...riscv-isa-release-ec3b886-2024-11-07

Release riscv-isa-release-152ef53-2024-11-06

This release was created by: aswaterman
Release of RISC-V ISA, built from commit 152ef53, is now available.

What's Changed

• Add vector CSRs to CSR table by @aswaterman in #1714

Full Changelog: riscv-isa-release-cc636c0-2024-11-04...riscv-isa-release-152ef53-2024-11-06

Release riscv-isa-release-d0d5c67-2024-11-04

This release was created by: aswaterman
Release of RISC-V ISA, built from commit d0d5c67, is now available.

What's Changed

• Add Ssqosid to extensions table in preface by @ved-rivos in #1707
• standardize "extension" suffix on extensions in priv preface by @aswaterman in #1708

Full Changelog: riscv-isa-release-6114bf9-2024-11-02...riscv-isa-release-d0d5c67-2024-11-04

Release riscv-isa-release-cc636c0-2024-11-04

This release was created by: aswaterman
Release of RISC-V ISA, built from commit cc636c0, is now available.

What's Changed

• Clarify note that compilers may need to change vtype for vmvr.v by @lukel97 in #1710

New Contributors

• @lukel97 made their first contribution in #1710

Full Changelog: riscv-isa-release-192eeeb-2024-11-04...riscv-isa-release-cc636c0-2024-11-04

Release riscv-isa-release-192eeeb-2024-11-04

This release was created by: aswaterman
Release of RISC-V ISA, built from commit 192eeeb, is now available.

What's Changed

• Add Ssqosid to extensions table in preface by @ved-rivos in #1707
• standardize "extension" suffix on extensions in priv preface by @aswaterman in #1708

Full Changelog: riscv-isa-release-6114bf9-2024-11-02...riscv-isa-release-192eeeb-2024-11-04

Release riscv-isa-release-6114bf9-2024-11-02

This release was created by: aswaterman
Release of RISC-V ISA, built from commit 6114bf9, is now available.

Release riscv-isa-release-e24a456-2024-10-28

This release was created by: aswaterman
Release of RISC-V ISA, built from commit e24a456, is now available.

What's Changed

• Improve table: Compressed instruction formats by @cousteaulecommandant in #1696

New Contributors

• @cousteaulecommandant made their first contribution in #1696

Full Changelog: riscv-isa-release-084b690-2024-10-22...riscv-isa-release-e24a456-2024-10-28

Release riscv-isa-release-34b6e75-2024-10-28

This release was created by: aswaterman
Release of RISC-V ISA, built from commit 34b6e75, is now available.

What's Changed

• Fix NOTE about ARM FMA mnemonics by @aswaterman in #1700

Full Changelog: riscv-isa-release-e24a456-2024-10-28...riscv-isa-release-34b6e75-2024-10-28

Release riscv-isa-release-084b690-2024-10-22

This release was created by: wmat
Release of RISC-V ISA, built from commit 084b690, is now available.

What's Changed

• Fix for issue 1693 (HSLEN should be HSXLEN) by @james-ball-qualcomm in #1694

New Contributors

• @james-ball-qualcomm made their first contribution in #1694

Full Changelog: riscv-isa-release-ae98787-2024-10-19...riscv-isa-release-084b690-2024-10-22

Release riscv-isa-release-ae98787-2024-10-19

This release was created by: aswaterman
Release of RISC-V ISA, built from commit ae98787, is now available.

What's Changed

• remove redundant 'rd == x0' by @kacouane in #1690

Full Changelog: riscv-isa-release-2c07aa2-2024-10-18...riscv-isa-release-ae98787-2024-10-19