RISC-V Privileged Architecture, version 20210915-Public-Review-draftn

This is a draft of the RISC-V Privileged Architecture for public review of version 1.12 of the Machine and Supervisor modules and Version 1.0 of the Hypervisor module.

Draft of Zihintpause extension for public review

zihintpause-public-review-draft-20201013

Update zihintpause.tex

Ratified versions of the RV32I and RV64I base ISAs and MAFDQC standard extensions

Main change in this release is that the A extension, v2.1, has been ratified.

RISC-V Specification Archive

This is an archive of older versions of the RISC-V specifications.

These specifications are out of date! For the most recent ratified versions of the spec, please click here. For the most recent unratified drafts, please click here.

Note that these archived PDFs are static artifacts, and the source code to rebuild them is not included as part of this release.

Ratified versions of the RV32I and RV64I base ISAs, MFDQC standard extensions, and Privileged Architecture (Machine/Supervisor/User) v1.11

Ratified-IMFDQC-and-Priv-v1.11

Added text to indicate this is the ratified 1.11 version of the spec.

Privileged Architecture Machine/Supervisor/User Ratification

This is the specification version of the Privileged Architecture's Machine, Supervisor, and User modes that is being voted on for ratification.

IMFDQC Ratification

This is the specification version of the base ISA and the M, F, D, Q, and C extensions that is being voted on for ratification.

draft-20180524001518-9981ad7

Added commentary on purpose of static rounding modes.

RISC-V User ISA, Release 2.2

riscv-user-2.2

Add compiled specs

RISC-V Privileged ISA, Version 1.10

riscv-priv-1.10

Add compiled specs