riscv-software-src · aswaterman · Jun 18, 2023 · Jun 17, 2023 · Jun 17, 2023 · Jun 17, 2023
diff --git a/README.md b/README.md
@@ -53,20 +53,6 @@ Spike supports the following RISC-V ISA features:
   - Zvfbfmin extension, v0.6
   - Zvfbfwma extension, v0.6
 
-As a Spike extension, the remainder of the proposed
-[Bit-Manipulation Extensions](https://github.com/riscv/riscv-bitmanip)
-is provided under the Spike-custom extension name _Xbitmanip_.
-These instructions (and, of course, the extension name) are not RISC-V
-standards.
-
-These proposed bit-manipulation extensions can be split into further
-groups: Zbp, Zbs, Zbe, Zbf, Zbc, Zbm, Zbr, Zbt. Note that Zbc is
-ratified, but the original proposal contained some extra instructions
-(64-bit carryless multiplies) which are captured here.
-
-To enable these extensions individually, use the Spike-custom
-extension names _XZbp_, _XZbs_, _XZbc_, and so on.
-
 Versioning and APIs
 -------------------
 

diff --git a/disasm/disasm.cc b/disasm/disasm.cc
@@ -2144,38 +2144,6 @@ void disassembler_t::add_instructions(const isa_parser_t* isa)
     }
   }
 
-  if (isa->extension_enabled(EXT_XZBP)) {
-    DEFINE_ITYPE_SHIFT(grevi);
-    DEFINE_ITYPE_SHIFT(gorci);
-    DEFINE_RTYPE(pack);
-    DEFINE_RTYPE(packh);
-    DEFINE_RTYPE(packu);
-    DEFINE_RTYPE(grev);
-    DEFINE_RTYPE(gorc);
-    DEFINE_RTYPE(xperm4);
-    DEFINE_RTYPE(xperm8);
-    DEFINE_RTYPE(xperm16);
-    DEFINE_RTYPE(xperm32);
-  }
-
-  if (isa->extension_enabled(EXT_XZBP) ||
-      isa->extension_enabled(EXT_XZBE) ||
-      isa->extension_enabled(EXT_XZBF)) {
-    if(isa->get_max_xlen() == 64) {
-      DEFINE_RTYPE(packw);
-    }
-  }
-
-  if (isa->extension_enabled(EXT_XZBT)) {
-    DEFINE_R3TYPE(cmix);
-    DEFINE_R3TYPE(fsr);
-    DEFINE_R3TYPE(fsri);
-    if(isa->get_max_xlen() == 64) {
-      DEFINE_R3TYPE(fsriw);
-      DEFINE_R3TYPE(fsrw);
-    }
-  }
-
   if (isa->extension_enabled(EXT_ZICBOM)) {
     DISASM_INSN("cbo.clean", cbo_clean, 0, {&base_only_address});
     DISASM_INSN("cbo.flush", cbo_flush, 0, {&base_only_address});
@@ -2252,7 +2220,7 @@ disassembler_t::disassembler_t(const isa_parser_t *isa)
 
   // next-highest priority: other instructions in same base ISA
   std::string fallback_isa_string = std::string("rv") + std::to_string(isa->get_max_xlen()) +
-    "gqchv_zfh_zba_zbb_zbc_zbs_zcb_zicbom_zicboz_zkn_zkr_zks_svinval_xbitmanip";
+    "gqchv_zfh_zba_zbb_zbc_zbs_zcb_zicbom_zicboz_zkn_zkr_zks_svinval";
   isa_parser_t fallback_isa(fallback_isa_string.c_str(), DEFAULT_PRIV);
   add_instructions(&fallback_isa);
 

diff --git a/riscv/insns/bcompress.h b/riscv/insns/bcompress.h
diff --git a/riscv/insns/bcompressw.h b/riscv/insns/bcompressw.h
diff --git a/riscv/insns/bdecompress.h b/riscv/insns/bdecompress.h
diff --git a/riscv/insns/bdecompressw.h b/riscv/insns/bdecompressw.h
diff --git a/riscv/insns/bfp.h b/riscv/insns/bfp.h
diff --git a/riscv/insns/bfpw.h b/riscv/insns/bfpw.h
diff --git a/riscv/insns/bmatflip.h b/riscv/insns/bmatflip.h
diff --git a/riscv/insns/bmator.h b/riscv/insns/bmator.h
diff --git a/riscv/insns/bmatxor.h b/riscv/insns/bmatxor.h
diff --git a/riscv/insns/clmulhw.h b/riscv/insns/clmulhw.h
diff --git a/riscv/insns/clmulrw.h b/riscv/insns/clmulrw.h
diff --git a/riscv/insns/clmulw.h b/riscv/insns/clmulw.h
diff --git a/riscv/insns/cmix.h b/riscv/insns/cmix.h
@@ -1,2 +1,2 @@
-require_either_extension(EXT_ZBPBO, EXT_XZBT);
+require_extension(EXT_ZBPBO);
 WRITE_RD((RS1 & RS2) | (RS3 & ~RS2));
diff --git a/riscv/insns/cmov.h b/riscv/insns/cmov.h
diff --git a/riscv/insns/crc32_b.h b/riscv/insns/crc32_b.h
diff --git a/riscv/insns/crc32_d.h b/riscv/insns/crc32_d.h
diff --git a/riscv/insns/crc32_h.h b/riscv/insns/crc32_h.h
diff --git a/riscv/insns/crc32_w.h b/riscv/insns/crc32_w.h
diff --git a/riscv/insns/crc32c_b.h b/riscv/insns/crc32c_b.h
diff --git a/riscv/insns/crc32c_d.h b/riscv/insns/crc32c_d.h
diff --git a/riscv/insns/crc32c_h.h b/riscv/insns/crc32c_h.h
diff --git a/riscv/insns/crc32c_w.h b/riscv/insns/crc32c_w.h
diff --git a/riscv/insns/fsl.h b/riscv/insns/fsl.h
diff --git a/riscv/insns/fslw.h b/riscv/insns/fslw.h
diff --git a/riscv/insns/fsr.h b/riscv/insns/fsr.h
@@ -1,4 +1,5 @@
-require_either_extension(xlen == 32 ? EXT_ZBPBO : EXT_XZBT, EXT_XZBT);
+require_rv32;
+require_extension(EXT_ZBPBO);
 int shamt = RS2 & (2*xlen-1);
 reg_t a = RS1, b = RS3;
 if (shamt >= xlen) {

diff --git a/riscv/insns/fsri.h b/riscv/insns/fsri.h
@@ -1,4 +1,5 @@
-require_either_extension(xlen == 32 ? EXT_ZBPBO : EXT_XZBT, EXT_XZBT);
+require_rv32;
+require_extension(EXT_ZBPBO);
 int shamt = SHAMT & (2*xlen-1);
 reg_t a = RS1, b = RS3;
 if (shamt >= xlen) {

diff --git a/riscv/insns/fsriw.h b/riscv/insns/fsriw.h
diff --git a/riscv/insns/fsrw.h b/riscv/insns/fsrw.h
@@ -1,5 +1,5 @@
 require_rv64;
-require_either_extension(EXT_ZBPBO, EXT_XZBT);
+require_extension(EXT_ZBPBO);
 int shamt = RS2 & 63;
 reg_t a = RS1, b = RS3;
 if (shamt >= 32) {

diff --git a/riscv/insns/gorc.h b/riscv/insns/gorc.h
diff --git a/riscv/insns/gorci.h b/riscv/insns/gorci.h
@@ -1,6 +1,5 @@
 // Zbb contains orc.b but not general gorci
-require(((SHAMT == 7) && p->extension_enabled(EXT_ZBB))
-  || p->extension_enabled(EXT_XZBP));
+require(((SHAMT == 7) && p->extension_enabled(EXT_ZBB)));
 require(SHAMT < xlen);
 reg_t x = RS1;
 int shamt = SHAMT;

diff --git a/riscv/insns/gorciw.h b/riscv/insns/gorciw.h
diff --git a/riscv/insns/gorcw.h b/riscv/insns/gorcw.h
diff --git a/riscv/insns/grev.h b/riscv/insns/grev.h
diff --git a/riscv/insns/grevi.h b/riscv/insns/grevi.h
@@ -4,8 +4,7 @@ int shamt = SHAMT;
 require(((shamt == xlen - 8) && (p->extension_enabled(EXT_ZBB) || p->extension_enabled(EXT_ZBKB))) //rev8
   || ((shamt == 7) && p->extension_enabled(EXT_ZBKB)) // rev8.b
   || ((shamt == 8) && p->extension_enabled(EXT_ZPN)) // rev8.h
-  || ((shamt == xlen - 1) && p->extension_enabled(EXT_ZPN)) // rev
-  || p->extension_enabled(EXT_XZBP));
+  || ((shamt == xlen - 1) && p->extension_enabled(EXT_ZPN)));
 require(shamt < xlen);
 reg_t x = RS1;
 if (shamt &  1) x = ((x & 0x5555555555555555LL) <<  1) | ((x & 0xAAAAAAAAAAAAAAAALL) >>  1);