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Pull requests: riscv-software-src/riscv-isa-sim
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medeleg: the third bit(CAUSE_BREAKPOINT) of medeleg is unwritable when Sdtrig exist.
#1742
opened Jul 23, 2024 by
NewPaulWalker
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Adjust wide_counter_csr_t::written_value() to only increment if counting is enabled, Bug Fix for PR 1381
#1581
opened Jan 24, 2024 by
rbuchner-aril
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Provide accessibility control of xcontext CSRs through stateen0[57] CSR
#1550
opened Dec 25, 2023 by
YenHaoChen
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triggers: implement {mcontrol,mcontrol6}.match = {not equal,not napot,not mask low,not mask high}
#1348
opened May 4, 2023 by
YenHaoChen
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workaround to support access to large 64-bit physical addresses
#1100
opened Sep 26, 2022 by
aap-sc
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