target/riscv: Add support for Sv57 (and Sv57x4) translation mode

[kr-sc]

Also fix Sv48x4 translation mode (riscv.c:224). According to riscv privileged specification, pa_ppn_mask in sv48x4 mode should be same as in sv48 mode.

[timsifive]

This looks good. What testing have you done?

[kr-sc]

I run this tests. Sv57 I check on spike + telnet + custom script for generate page table

spike32

test list

CeaseMultiTest CeaseRunTest CeaseStepiTest CheckMisa CustomRegisterTest DebugBreakpoint DebugChangeString DebugCompareSections DebugExit DebugFunctionCall DebugSymbols DebugTurbostep DisconnectTest DownloadTest EbreakTest EtriggerTest FreeRtosTest Hwbp1 Hwbp2 HwbpManual IcountTest InfoTest InstantChangePc InstantHaltTest InterruptTest ItriggerTest JumpHbreak MemTest16 MemTest32 MemTest64 MemTest8 MemTestBlock0 MemTestBlock1 MemTestBlock2 MemTestBlockReadInvalid MemTestReadInvalid MemorySampleMixed MemorySampleSingle MulticoreRegTest MulticoreRtosSwitchActiveHartTest MulticoreRunAllHaltOne PrivChange PrivRw ProgramHwWatchpoint ProgramSwWatchpoint Registers RepeatReadTest Semihosting SemihostingFileio SimpleF18Test SimpleNoExistTest SimpleS0Test SimpleS1Test SimpleT0Test SimpleT1Test SimpleV13Test SmpSimultaneousRunHalt StepTest StepThread2Test Sv32Test Sv39Test Sv48Test TooManyHwbp TriggerDmode TriggerExecuteInstant TriggerLoadAddressInstant TriggerStoreAddressInstant UserInterrupt VectorTest WriteCsrs WriteGprs

:::::::::::::::::::::::::::[ ran 71 tests in 190s ]:::::::::::::::::::::::::::
14 tests returned not_applicable
57 tests returned pass

spike64

test list

CeaseMultiTest CeaseRunTest CeaseStepiTest CheckMisa CustomRegisterTest DebugBreakpoint DebugChangeString DebugCompareSections DebugExit DebugFunctionCall DebugSymbols DebugTurbostep DisconnectTest DownloadTest EbreakTest EtriggerTest FreeRtosTest Hwbp1 Hwbp2 HwbpManual IcountTest InfoTest InstantChangePc InstantHaltTest InterruptTest ItriggerTest JumpHbreak MemTest16 MemTest32 MemTest64 MemTest8 MemTestBlock0 MemTestBlock1 MemTestBlock2 MemTestBlockReadInvalid MemTestReadInvalid MemorySampleMixed MemorySampleSingle MulticoreRegTest MulticoreRtosSwitchActiveHartTest MulticoreRunAllHaltOne PrivChange PrivRw ProgramHwWatchpoint ProgramSwWatchpoint Registers RepeatReadTest Semihosting SemihostingFileio SimpleF18Test SimpleNoExistTest SimpleS0Test SimpleS1Test SimpleT0Test SimpleT1Test SimpleV13Test SmpSimultaneousRunHalt StepTest StepThread2Test Sv32Test Sv39Test Sv48Test TooManyHwbp TriggerDmode TriggerExecuteInstant TriggerLoadAddressInstant TriggerStoreAddressInstant UserInterrupt VectorTest WriteCsrs WriteGprs

:::::::::::::::::::::::::::[ ran 71 tests in 202s ]:::::::::::::::::::::::::::
12 tests returned not_applicable
59 tests returned pass

spike32-2-hwthread

test list

CeaseMultiTest CeaseRunTest CeaseStepiTest CheckMisa CustomRegisterTest DebugBreakpoint DebugChangeString DebugCompareSections DebugExit DebugFunctionCall DebugSymbols DebugTurbostep DisconnectTest DownloadTest EbreakTest EtriggerTest FreeRtosTest Hwbp1 Hwbp2 HwbpManual IcountTest InfoTest InstantChangePc InstantHaltTest InterruptTest ItriggerTest JumpHbreak MemTest16 MemTest32 MemTest64 MemTest8 MemTestBlock0 MemTestBlock1 MemTestBlock2 MemTestBlockReadInvalid MemTestReadInvalid MemorySampleMixed MemorySampleSingle MulticoreRegTest MulticoreRtosSwitchActiveHartTest MulticoreRunAllHaltOne PrivChange PrivRw ProgramHwWatchpoint ProgramSwWatchpoint Registers RepeatReadTest Semihosting SemihostingFileio SimpleF18Test SimpleNoExistTest SimpleS0Test SimpleS1Test SimpleT0Test SimpleT1Test SimpleV13Test SmpSimultaneousRunHalt StepTest StepThread2Test Sv32Test Sv39Test Sv48Test TooManyHwbp TriggerDmode TriggerExecuteInstant TriggerLoadAddressInstant TriggerStoreAddressInstant UserInterrupt VectorTest WriteCsrs WriteGprs

:::::::::::::::::::::::::::[ ran 71 tests in 244s ]:::::::::::::::::::::::::::
12 tests returned not_applicable
59 tests returned pass

spike64-2

test list

CeaseMultiTest CeaseRunTest CeaseStepiTest CheckMisa CustomRegisterTest DebugBreakpoint DebugChangeString DebugCompareSections DebugExit DebugFunctionCall DebugSymbols DebugTurbostep DisconnectTest DownloadTest EbreakTest EtriggerTest FreeRtosTest Hwbp1 Hwbp2 HwbpManual IcountTest InfoTest InstantChangePc InstantHaltTest InterruptTest ItriggerTest JumpHbreak MemTest16 MemTest32 MemTest64 MemTest8 MemTestBlock0 MemTestBlock1 MemTestBlock2 MemTestBlockReadInvalid MemTestReadInvalid MemorySampleMixed MemorySampleSingle MulticoreRegTest MulticoreRtosSwitchActiveHartTest MulticoreRunAllHaltOne PrivChange PrivRw ProgramHwWatchpoint ProgramSwWatchpoint Registers RepeatReadTest Semihosting SemihostingFileio SimpleF18Test SimpleNoExistTest SimpleS0Test SimpleS1Test SimpleT0Test SimpleT1Test SimpleV13Test SmpSimultaneousRunHalt StepTest StepThread2Test Sv32Test Sv39Test Sv48Test TooManyHwbp TriggerDmode TriggerExecuteInstant TriggerLoadAddressInstant TriggerStoreAddressInstant UserInterrupt VectorTest WriteCsrs WriteGprs

:::::::::::::::::::::::::::[ ran 71 tests in 264s ]:::::::::::::::::::::::::::
14 tests returned not_applicable
57 tests returned pass

spike32-2

test list

CeaseMultiTest CeaseRunTest CeaseStepiTest CheckMisa CustomRegisterTest DebugBreakpoint DebugChangeString DebugCompareSections DebugExit DebugFunctionCall DebugSymbols DebugTurbostep DisconnectTest DownloadTest EbreakTest EtriggerTest FreeRtosTest Hwbp1 Hwbp2 HwbpManual IcountTest InfoTest InstantChangePc InstantHaltTest InterruptTest ItriggerTest JumpHbreak MemTest16 MemTest32 MemTest64 MemTest8 MemTestBlock0 MemTestBlock1 MemTestBlock2 MemTestBlockReadInvalid MemTestReadInvalid MemorySampleMixed MemorySampleSingle MulticoreRegTest MulticoreRtosSwitchActiveHartTest MulticoreRunAllHaltOne PrivChange PrivRw ProgramHwWatchpoint ProgramSwWatchpoint Registers RepeatReadTest Semihosting SemihostingFileio SimpleF18Test SimpleNoExistTest SimpleS0Test SimpleS1Test SimpleT0Test SimpleT1Test SimpleV13Test SmpSimultaneousRunHalt StepTest StepThread2Test Sv32Test Sv39Test Sv48Test TooManyHwbp TriggerDmode TriggerExecuteInstant TriggerLoadAddressInstant TriggerStoreAddressInstant UserInterrupt VectorTest WriteCsrs WriteGprs

:::::::::::::::::::::::::::[ ran 71 tests in 270s ]:::::::::::::::::::::::::::
13 tests returned not_applicable
58 tests returned pass

spike64-2-hwthread

test list

CeaseMultiTest CeaseRunTest CeaseStepiTest CheckMisa CustomRegisterTest DebugBreakpoint DebugChangeString DebugCompareSections DebugExit DebugFunctionCall DebugSymbols DebugTurbostep DisconnectTest DownloadTest EbreakTest EtriggerTest FreeRtosTest Hwbp1 Hwbp2 HwbpManual IcountTest InfoTest InstantChangePc InstantHaltTest InterruptTest ItriggerTest JumpHbreak MemTest16 MemTest32 MemTest64 MemTest8 MemTestBlock0 MemTestBlock1 MemTestBlock2 MemTestBlockReadInvalid MemTestReadInvalid MemorySampleMixed MemorySampleSingle MulticoreRegTest MulticoreRtosSwitchActiveHartTest MulticoreRunAllHaltOne PrivChange PrivRw ProgramHwWatchpoint ProgramSwWatchpoint Registers RepeatReadTest Semihosting SemihostingFileio SimpleF18Test SimpleNoExistTest SimpleS0Test SimpleS1Test SimpleT0Test SimpleT1Test SimpleV13Test SmpSimultaneousRunHalt StepTest StepThread2Test Sv32Test Sv39Test Sv48Test TooManyHwbp TriggerDmode TriggerExecuteInstant TriggerLoadAddressInstant TriggerStoreAddressInstant UserInterrupt VectorTest WriteCsrs WriteGprs

:::::::::::::::::::::::::::[ ran 71 tests in 326s ]:::::::::::::::::::::::::::
12 tests returned not_applicable
59 tests returned pass

[timsifive]

Sounds good. Could you extend https://github.com/riscv-software-src/riscv-tests/blob/d4eaa5bd6674b51d3b9b24913713c4638e99cdd9/debug/gdbserver.py#L1635 to also test Sv57? It already tests the other (non-x4) translation modes?

[kr-sc]

Extension for riscv-tests in progress, trying to figure out in infrastructure.

[timsifive]

Extension for riscv-tests in progress, trying to figure out in infrastructure.

Thanks. Let me know if you have any questions.