New Landscape Entry - Syntacore

[dmsh11]

Project Name

Syntacore

Description

Syntacore is a RISC-V processor IP specialist. We create flexible, highly-efficient microprocessor cores that help customers to design unique solutions for the IoT, data storage and processing, embedded systems, cognitive, machine learning and artificial intelligence applications.

Homepage URL

https://syntacore.com/

Crunchbase URL (https://www.crunchbase.com/)

https://www.crunchbase.com/organization/syntacore

Repository URL (Only if publicly available)

No response

Organization hosting or owning the project

Syntacore

Evidence of RISC-V ecosystem support

llvm/llvm-project#65599, llvm/llvm-project#67334
• fixed a bug with excessively long compilation for extractelement/insertelement, which occurred when RVV was disabled
debugger (OpenOCD)
• updated the debug specification with a mechanism for decoding system register values - riscv/riscv-debug-spec#858
• implemented support for inaccessible registers
• implemented Sv57 (and Sv57x4) translation mode - riscv-collab/riscv-openocd#904
runtimes
• backported MD5 to jdk17 and jdk21 - openjdk/jdk21u#209, openjdk/jdk17u-dev#1850
• OpenJDK: implemented several mathematical intrinsics: ceil, floor, rint, umulhi - openjdk/jdk#15558, openjdk/jdk#14991

Logo

Category

Processors

Sub-Category

Implementations -> IP

[github-actions]

Thank you for requesting a new entry to be added, @dmsh11!
Consider also adding this entry at RISC-V Exchange.

[github-actions]

Thank you for requesting a new entry to be added, @dmsh11!
Consider also adding this entry at RISC-V Exchange.

[rpsene]

@bprestonlf +1.

[andyjohnstonmoore]

@bprestonlf +1