Netlist

A netlist comprises of gates and nets and describes the connectivity of an electronic circuit. In hardware reverse engineering, a netlist may either be extracted from the images taken of each layer of an integrated circuit (IC) or from the bitstream of a field-programmable gate array (FPGA). The netlist itself can be interpreted as a graph with the gates representing its nodes and the nets representing their connections. Commonly, the netlist is stored as a Verilog or VHDL file. It can be parsed into HAL by using either the provided netlist parsers or writing a new one.

Netlist Information

In HAL, a netlist holds its ID, the path to the file the netlist has been read from, the name of the design, and the name of the targeted device. Additionally, it holds information about the underlying gate library and keeps track of all its gates and nets. From within Python, the currently opened netlist is simply available via netlist. The ID can be retrieved using get_id and set using set_id. To get or set the path to the input file, use get_input_filename or set_input_filename respectively. Access to the design name and target device is provided by get_design_name, set_design_name, get_device_name, and set_device_name. The gate library can be retrieved using get_gate_library.

id = netlist.get_id()                     # get the id of the netlist
name = netlist.get_design_name()          # get the name of the design
netlist.set_device_name("example_chip")   # set the name of the target device
gl = netlist.get_gate_library()           # get the underlying gate library

Furthermore, HAL provides the reverse engineer with the ability to add structure to the netlist during reversing. Therefore, modules provide an easy way for modularization and hierarchization of the design. Additionally, groupings can be used to temporarily store unordered sets of gates, nets, and modules during the reversing process. Both modules and groupings are actually part of the netlist and may be managed through functions provided by the netlist. These functions enable the creation, deletion, and retrieval of gates, nets, modules, and groupings and are described in the respective chapters.