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Creating a Gate Library
While HAL supports reading gate libraries in Liberty file format, it also comes with a custom gate library format that allows for additional information to be added to the gate library that aid the reverse engineering process. This includes annotations for gate type properties and pin types, that cannot fully be extracted from a Liberty gate library. This page describes this custom HAL gate library (.hgl) format, which is based on JSON syntax.
A gate library consists of a name, i.e., a unique identifier of the library, and a list of cells. Each cell again comes with a name, a list of properties (referred to as types below), and a list of pins. Optionally, it can also feature a list of pin groups or dedicated fields for flip-flops, latches, LUTs, and RAMs. Furthermore, the gate library may feature specifications on where location data of gates is found within the data fields of a gate. A simple example is shown below:
{
"library": "SOME_LIBRARY_NAME",
"gate_locations": {
"data_category": "generic",
"data_x_identifier": "X_COORDINATE",
"data_y_identifier": "Y_COORDINATE"
},
"cells": [
{
"name": "AND",
"types": [
"combinational"
],
"pins": [
{
"name": "A",
"direction": "input"
},
{
"name": "B",
"direction": "input"
},
{
"name": "O",
"direction": "output",
"function": "A & B"
}
]
},
{
"name": "WEIRD_GATE",
"types": [
"combinational"
],
"pins": [
{
"name": "A(0)",
"direction": "input"
},
{
"name": "A(1)",
"direction": "input"
},
{
"name": "A(2)",
"direction": "input"
},
{
"name": "A(3)",
"direction": "input"
},
{
"name": "O",
"direction": "output",
"function": "A(0) & A(1) & A(2) & A(3)"
}
],
"groups": [
{
"name": "A",
"pins": [
{
"0": "A(0)"
},
{
"1": "A(1)"
},
{
"2": "A(2)"
},
{
"3": "A(3)"
}
]
}
]
}
]
} {
"name": "LUT4",
"types": [
"combinational",
"lut"
],
"lut_config": {
"bit_order": "descending",
"data_category": "generic",
"data_identifier": "INIT"
},
"pins": [
{
"name": "I0",
"direction": "input"
},
{
"name": "I1",
"direction": "input"
},
{
"name": "I2",
"direction": "input"
},
{
"name": "I3",
"direction": "input"
},
{
"name": "O",
"direction": "output",
"type": "lut"
}
]
}, {
"name": "FFRSE",
"types": [
"sequential",
"ff"
],
"ff_config": {
"data_category": "generic",
"data_identifier": "INIT",
"state": "IQ",
"neg_state": "IQN",
"next_state": "D",
"clocked_on": "CE & C",
"clear_on": "CLR",
"preset_on": "PRE",
"state_clear_preset": "L",
"neg_state_clear_preset": "L"
},
"pins": [
{
"name": "C",
"direction": "input",
"type": "clock"
},
{
"name": "CE",
"direction": "input",
"type": "enable"
},
{
"name": "D",
"direction": "input",
"type": "data"
},
{
"name": "CLR",
"direction": "input",
"type": "reset"
},
{
"name": "PRE",
"direction": "input",
"type": "set"
},
{
"name": "Q",
"direction": "output",
"function": "IQ",
"type": "state"
},
{
"name": "QN",
"direction": "output",
"function": "IQN",
"type": "neg_state"
}
]
}, {
"name": "LDCE",
"types": [
"sequential",
"latch"
],
"latch_config": {
"state": "IQ",
"neg_state": "IQN",
"data_in": "D",
"enable_on": "GE",
"clear_on": "CLR",
"preset_on": "PRE",
"state_clear_preset": "L",
"neg_state_clear_preset": "L"
},
"pins": [
{
"name": "CLR",
"direction": "input"
},
{
"name": "D",
"direction": "input"
},
{
"name": "G",
"direction": "input"
},
{
"name": "GE",
"direction": "input"
},
{
"name": "CLR",
"direction": "input",
"type": "reset"
},
{
"name": "PRE",
"direction": "input",
"type": "set"
},
{
"name": "Q",
"direction": "output",
"function": "IQ",
"type": "state"
},
{
"name": "QN",
"direction": "output",
"function": "IQN",
"type": "neg_state"
}
]
},