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Logic Evaluator
The logic evaluator is aimed to help the understanding of netlists or part of the netlists where only combinatorical logic is involved. The focus of the tool is to provide a user friendly handle to test the logic with various input combinations and to visualize the results. It will also try to detect module- or gate pingroups at input or output.
The plugin is not part of the current master yet. It is available through branch feature/logic_evaluator. For on-demand compilation a gcc compiler is required in search path.
The logic evaluator can be launched from the graphical view context menu (right click) after having selected the gates to be analyzed. The selected combinatoric gates and combinatoric gates comprised by selected modules will be considered as subnet. The output signals of this subnet will be generated by evaluating the boolean functions on given input.
Gates must not carry the ff, latch, or ram property in order to qualify for evaluation. For all other gates it is the responsibility of the user to make sure the logic is well defined by having a valid boolean function assigned to each relevant output in associated gate library.
The logic evaluator can also be launched from the GUI Plugin Manager page by clicking on the GUI extension of the logic evaluator plugin. If no gates are selected a tree view will open to the select the gates to be evaluated.
Since the Logic Evaluator acts as a modeless dialog the user can continue to work with HAL while the Logic Evaluator widget is open. Obviously it is not advised to delete nets or gates which are part of the evaluation. However, while running the Logic Evaluator does not care about modules as they get only accessed at launch time.
It is safe to run multiple Logic Evaluators at the same time.
- By default all input signals are set to zero indicated by blue checkbox. Click a box to toggle the input.
- Input groups have an additional spinbox. Enter a hex value into the spinbox or use small buttons to increase or decrease the value.
- Menu Entry 'Options'
- A checkbox controls whether evaluation is done by compiled bitcode or by running
BooleanLogic::eval()for each output pin (see below). - A checkbox controls whether the results of the evaluation are indicated by grouping colors in the graphical netlist view.
- A checkbox controls whether evaluation is done by compiled bitcode or by running
- Menu Entry 'Relaunch' launches a tree view to select gates for another logic evaluator.
- Menu Entry 'Truth Table' launches a truth table to evaluate all possible input combinations.
The 'Relaunch' allows to select a new set of gates to launch another logic evaluator. The tree view shows all gates of the netlist as they are organized in modules. However, only eligible gates have a checkbox in front of them. The user can also toggle the checkbox in front of a module to select or deselect all gates from this module.
Underneath the tree view the standard HAL Searchbar widget can be used to filter gates shown in tree view. Gates might still be selected even when not shown because of filter setting. If only gates passing the filter should be part of the evaluation it is recommended to clear the selection first by removing the check marker in front of the top_module.
The 'Truth Table' lists the output signals for all possible input combinations. The table values be visualized by digits (0/1), letters (L/H), or color (blue/red). It is possible to sort the table by either clicking on a signal or defining up to 5 signals as sort keys. Double click on a column header (single combination) closes the truth table and puts this combination into the logic evaluator.
At this point of time we have no experience concerning the performance when evaluating large netlists. When run in compiled mode the tool will try to create a sequential Ansi-C code, compile this code and load the bitcode as a temporary shared library. The tool will be set into pure evaluation mode where all output pins gets evaluated using the HAL function BooleanLogic::eval() if
- Compilation was omitted when launching the tool
- The ckeckbox "Run compiled logic" gets unchecked
- Compilation or loading of shared library failed
By checking "Show in graphic view" the states of all evaluated nets are shown by grouping colors. That works best if all selections have been cleared.