New: Put in place SUPERVISOR, HYPERVISOR and USER mode enable parameters

New: Add documentation on privilege modes, description and design Change: Rework MSTATUS, aligning it with latest privilege spec and create a function to format it
dpretet · Sep 9, 2023 · dbe0aa2 · dbe0aa2
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diff --git a/doc/ios_params.md b/doc/ios_params.md
@@ -50,6 +50,21 @@
     - 0 or 1
     - default: 0, no multiply/divide support
 
+- USER_MODE
+    - activate user mode support
+    - 0 or 1
+    - default: 0, not supported
+
+- SUPERVISOR_MODE
+    - activate supervisor mode support
+    - 0 or 1
+    - default: 0, not supported
+
+- HYPERVISOR_MODE
+    - activate hypervisor mode support
+    - 0 or 1
+    - default: 0, not supported
+
 - PROCESSING_BUS_PIPELINE
     - insert a pipeline at processing unit input bus
     - 0 or 1

diff --git a/doc/monodraw.monopic b/doc/monodraw.monopic
diff --git a/doc/privilege.md b/doc/privilege.md
@@ -0,0 +1,72 @@
+# Privilege Modes Support
+
+FRISCV supports machine mode as default mode. it's always implemented as required by the
+specification. The core can also support user, supervisor and hypervisor modes, activable 
+all by paramters, `USER_MODE`, `SUPERVISOR_MODE`, `HYPERVISOR_MODE`.
+
+All modes use the same `XLEN` width. If `XLEN` = 32 bits, `MXLEN`, `SXLEN`, `UXLEN` and 
+`HXLEN` will be setup to 32 bits.
+
+The software navigates through the privilege levels with ECALL / xRET instructions
+
+```
+                   ┌────────────────────────────────┐   
+                   │            MACHINE             │   
+                   └────────────────────────────────┘   
+                        │                     ▲         
+                 MRET   │                     │  ECALL  
+                        ▼                     │         
+                   ┌────────────────────────────────┐   
+                   │           SUPERVISOR           │   
+                   └────────────────────────────────┘   
+                        │                     ▲         
+                 SRET   │                     │   ECALL 
+                        ▼                     │         
+                   ┌────────────────────────────────┐   
+                   │              USER              │   
+                   └────────────────────────────────┘   
+```
+
+CSR registers address encodes inner attributes:
+
+```
+                11/10      9/8         7/4         3/0     
+              ┌───────┬───────────┬───────────┬───────────┐
+              │  R/W  │ Privilege │    Use    │  Address  │
+              └───────┴───────────┴───────────┴───────────┘
+```
+
+Bit[11:10]:
+- `11`: read-only
+- Others: read/write
+
+Bits [9:8]:
+- `00`: User
+- `01`: Supervisor
+- `10`: Hypervisor
+- `11`: Machine
+
+
+# TODO
+
+Plan:
+- 1. user mode
+- 2. supervisor mode + virtual memory support
+- 3. hypervisor mode
+- 4. debug mode
+
+1. user mode
+
+- Support interrupts
+    - disable them for lower mode. If is SUPERVISOR, USER interrupts are disabled
+    - interrupts for higher mode are enabled, whatever xIE bit. If is SUPERVISOR, 
+      HYPERVISOR interrupt are enabled
+    - previous privilege mode interrupt is stored in xPP to support nested trap
+    - medeleg & mideleg
+        - delegate an trap to a mode means this mode can handle it. Traps never transition from
+          a more-privileged mode to a less-privileged mode (page 45)
+- Implement MSTATUS
+- Support virtual memory for supervisor mode (TVM correct support)
+- Support timer extension for each modes
+- Support priv mode in cache stages
+- V & F extensions support: XS, FS, VS fields