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Fix: yosys flow missed source file after parameter defaults'
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dpretet committed Dec 11, 2023
1 parent fda5b2a commit 8f0428b
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Showing 2 changed files with 2 additions and 0 deletions.
1 change: 1 addition & 0 deletions syn/yosys/friscv_rv32i.ys
Original file line number Diff line number Diff line change
Expand Up @@ -14,6 +14,7 @@ read -sv2012 ../../rtl/friscv_ram.sv
read -sv2012 ../../rtl/friscv_rambe.sv
read -sv2012 ../../rtl/friscv_icache.sv
read -sv2012 ../../rtl/friscv_dcache.sv
read -sv2012 ../../rtl/friscv_cache_prefetcher.sv
read -sv2012 ../../rtl/friscv_cache_io_fetcher.sv
read -sv2012 ../../rtl/friscv_cache_block_fetcher.sv
read -sv2012 ../../rtl/friscv_cache_ooo_mgt.sv
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1 change: 1 addition & 0 deletions syn/yosys/syn_x7.sh
Original file line number Diff line number Diff line change
Expand Up @@ -18,6 +18,7 @@ SRCS="\
../../rtl/friscv_rambe.sv \
../../rtl/friscv_icache.sv \
../../rtl/friscv_dcache.sv \
../../rtl/friscv_cache_prefetcher.sv \
../../rtl/friscv_cache_io_fetcher.sv \
../../rtl/friscv_cache_block_fetcher.sv \
../../rtl/friscv_cache_ooo_mgt.sv \
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