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Fix syn fileset
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@dpretet
dpretet committed Aug 14, 2023
1 parent 91a1ba1 commit 7e0287b
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Showing 12 changed files with 182 additions and 159 deletions.
5 changes: 1 addition & 4 deletions rtl/friscv_cache_blocks.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -75,9 +75,6 @@ module friscv_cache_blocks
// Number of isntruction per block, used to parse the words to write
localparam NB_INST_PER_BLK = CACHE_BLOCK_W / WLEN;

// Cache block width, tag + data + set bit
localparam FULL_BLOCK_W = CACHE_BLOCK_W + TAG_W + 1;


//////////////////////////////////////////////////////////////////////////
// Logic declaration
Expand Down Expand Up @@ -293,7 +290,7 @@ module friscv_cache_blocks
if (p2_ren) begin
p2_hit <= (p2_rblock_set && p2_rtag==p2_rblock_tag);
p2_miss <= (~p2_rblock_set || p2_rtag!=p2_rblock_tag);
p2_rdata <= p1_rblock_data[p2_roffset*WLEN+:WLEN];
p2_rdata <= p2_rblock_data[p2_roffset*WLEN+:WLEN];
`ifdef TRACE_BLOCKS
`trace_read(2)
`endif
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5 changes: 2 additions & 3 deletions rtl/friscv_cache_memctrl.sv
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Expand Up @@ -292,16 +292,15 @@ module friscv_cache_memctrl
///////////////////////////////////////////////////////////////////////////
// Read completion channel, used also as a cache block write interface
//
// Add extra signals for cache write purpose:
// Add extra signals for OoO Mgt / cache write purpose:
//
// - raddr: the original ARADDR of the request to drive cache write interface
// - rcache: ARCACHE[1], used to drive IO request to cache completion
// channel and so bypass the cache blocks
// - rdata_blk: the whole address line fetched, the controller always
// read a whole block
// - rdata: RDATA extracted from the interface to match the exact address
// while we always fetch a whole cache block. Make the controller usable
// for both instruction and data cache
// while we always fetch a whole cache block.
///////////////////////////////////////////////////////////////////////////

assign mst_rvalid = mem_rvalid;
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18 changes: 9 additions & 9 deletions rtl/friscv_dcache.sv
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Expand Up @@ -237,9 +237,9 @@ module friscv_dcache
logic [AXI_ID_W -1:0] pusher_bid;
logic [2 -1:0] pusher_bresp;
// cache write interface
logic cache_wren;
logic [AXI_ADDR_W -1:0] cache_waddr;
logic [CACHE_BLOCK_W -1:0] cache_wdata;
logic flush_wren;
logic [AXI_ADDR_W -1:0] flush_waddr;
logic [CACHE_BLOCK_W -1:0] flush_wdata;

// flag from prefetch to indicate the cache-miss block is under Write
logic block_fill;
Expand Down Expand Up @@ -617,10 +617,10 @@ module friscv_dcache
.aresetn (aresetn),
.srst (srst),
.flush (flushing),
.p1_wen (memctrl_rvalid & !memctrl_rcache | cache_wren),
.p1_wen (memctrl_rvalid & !memctrl_rcache | flush_wren),
.p1_wstrb ({CACHE_BLOCK_W/8{1'b1}}),
.p1_waddr ((cache_wren) ? cache_waddr : memctrl_raddr),
.p1_wdata ((cache_wren) ? cache_wdata : memctrl_rdata_blk),
.p1_waddr ((flush_wren) ? flush_waddr : memctrl_raddr),
.p1_wdata ((flush_wren) ? flush_wdata : memctrl_rdata_blk),
.p1_ren (fetcher_cache_ren),
.p1_raddr (fetcher_cache_raddr),
.p1_rdata (fetcher_cache_rdata),
Expand Down Expand Up @@ -654,9 +654,9 @@ module friscv_dcache
.flush_blocks (1'b0),
.flush_ack (),
.flushing (flushing),
.cache_wren (cache_wren),
.cache_waddr (cache_waddr),
.cache_wdata (cache_wdata)
.cache_wren (flush_wren),
.cache_waddr (flush_waddr),
.cache_wdata (flush_wdata)
);


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8 changes: 4 additions & 4 deletions rtl/friscv_dpram.sv
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Expand Up @@ -39,11 +39,11 @@ module friscv_dpram
end
end

generate if (FFD_EN==1) begin
generate if (FFD_EN==1) begin : SYNC_P1_RD
always @ (posedge aclk) begin
p1_data_out <= ram[p1_addr];
end
end else begin
end else begin : ASYNC_P1_RD
assign p1_data_out = ram[p1_addr];
end
endgenerate
Expand All @@ -54,11 +54,11 @@ module friscv_dpram
end
end

generate if (FFD_EN==1) begin
generate if (FFD_EN==1) begin : SYNC_P2_RD
always @ (posedge aclk) begin
p2_data_out <= ram[p2_addr];
end
end else begin
end else begin : ASYNC_P2_RD
assign p2_data_out = ram[p2_addr];
end
endgenerate
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8 changes: 4 additions & 4 deletions rtl/friscv_dprambe.sv
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Expand Up @@ -43,11 +43,11 @@ module friscv_dprambe
end
end

generate if (FFD_EN==1) begin
generate if (FFD_EN==1) begin : SYNC_P1_RD
always @ (posedge aclk) begin
p1_data_out <= ram[p1_addr];
end
end else begin
end else begin : ASYNC_P1_RD
assign p1_data_out = ram[p1_addr];
end
endgenerate
Expand All @@ -60,11 +60,11 @@ module friscv_dprambe
end
end

generate if (FFD_EN==1) begin
generate if (FFD_EN==1) begin : SYNC_P2_RD
always @ (posedge aclk) begin
p2_data_out <= ram[p2_addr];
end
end else begin
end else begin : ASYNC_P2_RD
assign p2_data_out = ram[p2_addr];
end
endgenerate
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19 changes: 14 additions & 5 deletions rtl/friscv_memfy.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -53,15 +53,15 @@ module friscv_memfy
parameter AXI_ID_MASK = 'h20,
// Select the ordering scheme:
// - 0: ongoing reads block write request, ongoing writes block read request
// - 1: concurrent r/w requests can be issued if don't target same cache blocks
// - 1: concurrent r/w requests can be issued if don't target the same address
parameter AXI_ORDERING = 0,
// Block width defining only the data payload, in bits, must an
// integer multiple of XLEN (power of two)
parameter DCACHE_BLOCK_W = XLEN*4,
// Maximum outstanding request supported
parameter MAX_OR = 8,
// Add pipeline on Rd write stage
parameter SYNC_RD_WR = 1,
parameter SYNC_RD_WR = 0,
// IO regions for direct read/write access
parameter IO_MAP_NB = 1,
// IO address ranges, organized by memory region as END-ADDR_START-ADDR:
Expand Down Expand Up @@ -505,11 +505,11 @@ module friscv_memfy

`ifdef TRACE_MEMFY
if (aresetn && arvalid && arready)
$fwrite(f, "(@ %0t) Read address %x\n", $realtime, araddr);
$fwrite(f, "(@ %0t) Read address : 0x%x\n", $realtime, araddr);
if (aresetn && awvalid && awready)
$fwrite(f, "(@ %0t) Write address %x\n", $realtime, awaddr);
$fwrite(f, "(@ %0t) Write address : 0x%x\n", $realtime, awaddr);
if (aresetn && wvalid && wready)
$fwrite(f, "(@ %0t) Write data %x / %0x\n", $realtime, wdata, wstrb);
$fwrite(f, "(@ %0t) Write data : 0x%x (0x%0x)\n", $realtime, wdata, wstrb);
`endif

end
Expand Down Expand Up @@ -664,6 +664,15 @@ module friscv_memfy
if (!aresetn) begin
memfy_exceptions[`LD_MA] <= '0;
end else begin
`ifdef TRACE_MEMFY

if (load_misaligned)
$fwrite(f, "(@ %0t) Exception encountered: Load misaligned\n", $realtime);

if (store_misaligned)
$fwrite(f, "(@ %0t) Exception encountered: store misaligned\n", $realtime);

`endif
memfy_exceptions[`LD_MA] <= load_misaligned;
memfy_exceptions[`ST_MA] <= store_misaligned;
end
Expand Down
144 changes: 112 additions & 32 deletions rtl/friscv_registers.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -76,12 +76,63 @@ module friscv_registers
input wire [XLEN -1:0] csr_rd_val
);

//------------------------------------------------
// Function to print register name and information
// @i: register number to get info
// @returns a string describing the register
//------------------------------------------------
function string get_name(integer i);
get_name = "!?";
if (i== 0) get_name = " zero (hardwired zero)";
if (i== 1) get_name = " ra (return address)";
if (i== 2) get_name = " sp (stack pointer)";
if (i== 3) get_name = " gp (global pointer)";
if (i== 4) get_name = " tp (thread pointer)";
if (i== 5) get_name = " t0 (temporary register 0)";
if (i== 6) get_name = " t1 (temporary register 0)";
if (i== 7) get_name = " t2 (temporary register 0)";
if (i== 8) get_name = " s0_fp (saved register 0 / frame pointer)";
if (i== 9) get_name = " s1 (saved register 1)";
if (i==10) get_name = " a0 (function argument 0 / return value 0)";
if (i==11) get_name = " a1 (function argument 1 / return value 1)";
if (i==12) get_name = " a2 (function argument 2)";
if (i==13) get_name = " a3 (function argument 3)";
if (i==14) get_name = " a4 (function argument 4)";
if (i==15) get_name = " a5 (function argument 5)";
if (i==16) get_name = " a6 (function argument 6)";
if (i==17) get_name = " a7 (function argument 7)";
if (i==18) get_name = " s2 (saved register 2)";
if (i==19) get_name = " s3 (saved register 3)";
if (i==20) get_name = " s4 (saved register 4)";
if (i==21) get_name = " s5 (saved register 5)";
if (i==22) get_name = " s6 (saved register 6)";
if (i==23) get_name = " s7 (saved register 7)";
if (i==24) get_name = " s8 (saved register 8)";
if (i==25) get_name = " s9 (saved register 9)";
if (i==26) get_name = " s10 (saved register 10)";
if (i==27) get_name = " s11 (saved register 11)";
if (i==28) get_name = " t3 (temporary register 3)";
if (i==29) get_name = " t4 (temporary register 4)";
if (i==30) get_name = " t5 (temporary register 5)";
if (i==31) get_name = " t6 (temporary register 6)";
endfunction


// E extension limiting the register number to 16
localparam REGNUM = (RV32E) ? 16 : 32;

// ISA registers 0-31
logic [XLEN-1:0] regs [REGNUM-1:0];

// Tracer setup
`ifdef TRACE_REGISTERS
integer f;
string fname;
initial begin
$sformat(fname, "trace_%s.txt", "registers");
f = $fopen(fname, "w");
end
`endif

generate

Expand Down Expand Up @@ -120,7 +171,7 @@ module friscv_registers
end else if (csr_rd_wr && csr_rd_addr==i) begin
regs[i] = csr_rd_val;

// Access from data memory controller
// Access from processing units
end else if (|proc_rd_wr) begin
for (u=0;u<NB_ALU_UNIT;u=u+1) begin
if (proc_rd_wr[u] && proc_rd_addr[u*5+:5]==i) begin
Expand All @@ -135,9 +186,37 @@ module friscv_registers
end
end

`ifdef TRACE_REGISTERS
always @ (posedge aclk) begin
if (aresetn) begin

if (ctrl_rd_wr && ctrl_rd_addr==i)
$fwrite(f, "(@ %0t) Ctrl Write : reg[%2d] = 0x%x (0xf) %s\n", $realtime, i, ctrl_rd_val, get_name(i));

if (csr_rd_wr && csr_rd_addr==i)
$fwrite(f, "(@ %0t) CSR Write : reg[%2d] = 0x%x (0xf) %s\n", $realtime, i, csr_rd_val, get_name(i));

for (u=0;u<NB_ALU_UNIT;u=u+1) begin
if (proc_rd_wr[u] && proc_rd_addr[u*5+:5]==i) begin

if (u==0)
$fwrite(f, "(@ %0t) ALU Write : reg[%2d] = 0x%x (0x%x) %s\n", $realtime, i, proc_rd_val[u*XLEN+:XLEN], proc_rd_strb[u*XLEN/8+:XLEN/8], get_name(i));
else if (u==1)
$fwrite(f, "(@ %0t) Memfy Write : reg[%2d] = 0x%x (0x%x) %s\n", $realtime, i, proc_rd_val[u*XLEN+:XLEN], proc_rd_strb[u*XLEN/8+:XLEN/8], get_name(i));
else if (u==2)
$fwrite(f, "(@ %0t) M_Ext Write : reg[%2d] = 0x%x (0x%x) %s\n", $realtime, i, proc_rd_val[u*XLEN+:XLEN], proc_rd_strb[u*XLEN/8+:XLEN/8], get_name(i));
else
$fwrite(f, "(@ %0t) Ext%d Write : reg[%2d] = 0x%x (0x%x) %s\n", $realtime, u, i, proc_rd_val[u*XLEN+:XLEN], proc_rd_strb[u*XLEN/8+:XLEN/8], get_name(i));

end
end
end
end
`endif
end
endgenerate


generate

if (SYNC_READ==0) begin: COMB_READ
Expand Down Expand Up @@ -184,37 +263,38 @@ module friscv_registers
end
endgenerate

assign x1_ra = regs[1];
assign x2_sp = regs[2];
assign x3_gp = regs[3];
assign x4_tp = regs[4];
assign x5_t0 = regs[5];
assign x6_t1 = regs[6];
assign x7_t2 = regs[7];
assign x8_s0_fp = regs[8];
assign x9_s1 = regs[9];
assign x10_a0 = regs[10];
assign x11_a1 = regs[11];
assign x12_a2 = regs[12];
assign x13_a3 = regs[13];
assign x14_a4 = regs[14];
assign x15_a5 = regs[15];
assign x16_a6 = regs[16];
assign x17_a7 = regs[17];
assign x18_s2 = regs[18];
assign x19_s3 = regs[19];
assign x20_s4 = regs[20];
assign x21_s5 = regs[21];
assign x22_s6 = regs[22];
assign x23_s7 = regs[23];
assign x24_s8 = regs[24];
assign x25_s9 = regs[25];
assign x26_s10 = regs[26];
assign x27_s11 = regs[27];
assign x28_t3 = regs[28];
assign x29_t4 = regs[29];
assign x30_t5 = regs[30];
assign x31_t6 = regs[31];
// Debug purpose only
assign x1_ra = regs[1];
assign x2_sp = regs[2];
assign x3_gp = regs[3];
assign x4_tp = regs[4];
assign x5_t0 = regs[5];
assign x6_t1 = regs[6];
assign x7_t2 = regs[7];
assign x8_s0_fp = regs[8];
assign x9_s1 = regs[9];
assign x10_a0 = regs[10];
assign x11_a1 = regs[11];
assign x12_a2 = regs[12];
assign x13_a3 = regs[13];
assign x14_a4 = regs[14];
assign x15_a5 = regs[15];
assign x16_a6 = regs[16];
assign x17_a7 = regs[17];
assign x18_s2 = regs[18];
assign x19_s3 = regs[19];
assign x20_s4 = regs[20];
assign x21_s5 = regs[21];
assign x22_s6 = regs[22];
assign x23_s7 = regs[23];
assign x24_s8 = regs[24];
assign x25_s9 = regs[25];
assign x26_s10 = regs[26];
assign x27_s11 = regs[27];
assign x28_t3 = regs[28];
assign x29_t4 = regs[29];
assign x30_t5 = regs[30];
assign x31_t6 = regs[31];

endmodule

Expand Down
1 change: 1 addition & 0 deletions syn/friscv_rv32i.ys
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Original file line number Diff line number Diff line change
Expand Up @@ -8,6 +8,7 @@ read -sv2012 ../rtl/friscv_alu.sv
read -sv2012 ../rtl/friscv_control.sv
read -sv2012 ../rtl/friscv_decoder.sv
read -sv2012 ../rtl/friscv_memfy.sv
read -sv2012 ../rtl/friscv_memfy_ordering.sv
read -sv2012 ../rtl/friscv_processing.sv
read -sv2012 ../rtl/friscv_bus_perf.sv
read -sv2012 ../rtl/friscv_scfifo.sv
Expand Down
3 changes: 2 additions & 1 deletion test/apps/run.sh
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Expand Up @@ -30,12 +30,13 @@ TB_CHOICE=1
# Don't assert a testbench error if X31 is asserted
ERROR_STATUS_X31=0

TRACE_CONTROL=0
TRACE_CONTROL=1
TRACE_CACHE=1
TRACE_BLOCKS=1
TRACE_FETCHER=1
TRACE_PUSHER=1
TRACE_MEMFY=1
TRACE_REGISTERS=1
TRACE_TB_RAM=1

# Disable external IRQ generation
Expand Down
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