Rework synthesis flow

README.md

@@ -81,6 +81,21 @@ The core is verified with several testsuites, present in [test](./test) folder:
 - [RISCV toolchain](https://github.com/riscv-collab/riscv-gnu-toolchain)
 
 
+## Performance
+
+[Coremark](test/apps/coremark) has been performed on the `platform` (core with caches + AXI interconnect and peripherals).
+The IP demonstrates 2.87 coremark / MHz:
+
+```
+CoreMark 1.0 : 1435 / GCC 11.1.1 -O1
+```
+
+## Synthesis & Area
+
+The core is usually synthesized with [Yosys](syn/yosys) during [continuous integration](https://github.com/dpretet/friscv/actions).
+to ensure. Follows area figured out by a synthesis with `Vivado 2021`:
+
+
 ## Validation environment
 
 The core has not been yet tested on hardware, but a synthesis flow based in [Yosys](https://github.com/YosysHQ/yosys)

doc/project_mgt_sw.md

@@ -16,6 +16,7 @@
         - [ ] https://fabiensanglard.net/another_world_polygons/
     - [ ] Hash table https://github.com/PerformanC/tablec/tree/closed-addressing
     - [ ] Dhrystone https://github.com/Keith-S-Thompson/dhrystone
+    - [ ] Embench https://github.com/embench/embench-iot
 
 # BACKLOG
 

flow.sh

@@ -253,10 +253,25 @@ main() {
     fi
 
     if [[ $1 == "syn" ]]; then
+
+        ret=0
+
         printinfo "Start synthesis flow"
-        cd "$FRISCV_DIR/syn"
-        ./syn_asic.sh
-        return $?
+        cd "$FRISCV_DIR/syn/yosys"
+
+        echo "------------------------------------"
+        echo " Run ASIC synthesis"
+        echo "------------------------------------"
+        ./syn_asic.sh | tee "$FRISCV_DIR/syn_asic.log"
+        ret=$((ret+$?))
+
+        echo "------------------------------------"
+        echo " Run Xilinx XC7 synthesis"
+        echo "------------------------------------"
+        ./syn_x7.sh | tee "$FRISCV_DIR/syn_x7.log"
+        ret=$((ret+$?))
+
+        return $ret
     fi
 }
 

syn/yosys/.gitignore

@@ -0,0 +1,3 @@
+*.v
+*.log
+*.history

syn/yosys/friscv_rv32i.ys

@@ -0,0 +1,53 @@
+# read design modules
+read -define XLEN=32
+read -incdir ../../rtl
+read -sv2012 ../../rtl/friscv_csr.sv
+read -sv2012 ../../rtl/friscv_registers.sv
+read -sv2012 ../../rtl/friscv_alu.sv
+read -sv2012 ../../rtl/friscv_control.sv
+read -sv2012 ../../rtl/friscv_decoder.sv
+read -sv2012 ../../rtl/friscv_memfy.sv
+read -sv2012 ../../rtl/friscv_processing.sv
+read -sv2012 ../../rtl/friscv_bus_perf.sv
+read -sv2012 ../../rtl/friscv_scfifo.sv
+read -sv2012 ../../rtl/friscv_ram.sv
+read -sv2012 ../../rtl/friscv_rambe.sv
+read -sv2012 ../../rtl/friscv_icache.sv
+read -sv2012 ../../rtl/friscv_dcache.sv
+read -sv2012 ../../rtl/friscv_cache_io_fetcher.sv
+read -sv2012 ../../rtl/friscv_cache_block_fetcher.sv
+read -sv2012 ../../rtl/friscv_cache_ooo_mgt.sv
+read -sv2012 ../../rtl/friscv_cache_pusher.sv
+read -sv2012 ../../rtl/friscv_cache_flusher.sv
+read -sv2012 ../../rtl/friscv_cache_blocks.sv
+read -sv2012 ../../rtl/friscv_cache_memctrl.sv
+read -sv2012 ../../rtl/friscv_bit_sync.sv
+read -sv2012 ../../rtl/friscv_checkers.sv
+read -sv2012 ../../rtl/friscv_div.sv
+read -sv2012 ../../rtl/friscv_m_ext.sv
+read -sv2012 ../../rtl/friscv_pipeline.sv
+read -sv2012 ../../rtl/friscv_rv32i_core.sv
+read -sv2012 ../../rtl/friscv_axi_or_tracker.sv
+read -sv2012 ../../rtl/friscv_mpu.sv
+read -sv2012 ../../rtl/friscv_pmp_region.sv
+read -sv2012 ../../rtl/friscv_pulser.sv
+
+# synthsize the core
+synth -top friscv_rv32i_core
+
+# convert design to (logical) gate-level netlists
+# +/adff2dff.v convert async reset to sync reset, used to mapp FFD correctly
+techmap +/adff2dff.v; opt
+# dffunmap
+
+# map internal register types to the ones from the cell library
+dfflibmap -liberty cmos.lib
+
+# use ABC to map remaining logic to cells from the cell library
+abc -liberty cmos.lib
+
+# cleanup
+clean
+
+# write synthesized design
+write_verilog friscv32i.v

syn/yosys/syn_x7.sh

@@ -0,0 +1,46 @@
+#!/usr/bin/env bash
+
+# -e: exit if one command fails
+# -o pipefail: causes a pipeline to fail if any command fails
+set -e -o pipefail
+
+SRCS="\
+../../rtl/friscv_csr.sv \
+../../rtl/friscv_registers.sv \
+../../rtl/friscv_alu.sv \
+../../rtl/friscv_control.sv \
+../../rtl/friscv_decoder.sv \
+../../rtl/friscv_memfy.sv \
+../../rtl/friscv_processing.sv \
+../../rtl/friscv_bus_perf.sv \
+../../rtl/friscv_scfifo.sv \
+../../rtl/friscv_ram.sv \
+../../rtl/friscv_rambe.sv \
+../../rtl/friscv_icache.sv \
+../../rtl/friscv_dcache.sv \
+../../rtl/friscv_cache_io_fetcher.sv \
+../../rtl/friscv_cache_block_fetcher.sv \
+../../rtl/friscv_cache_ooo_mgt.sv \
+../../rtl/friscv_cache_pusher.sv \
+../../rtl/friscv_cache_flusher.sv \
+../../rtl/friscv_cache_blocks.sv \
+../../rtl/friscv_cache_memctrl.sv \
+../../rtl/friscv_bit_sync.sv \
+../../rtl/friscv_checkers.sv \
+../../rtl/friscv_div.sv \
+../../rtl/friscv_m_ext.sv \
+../../rtl/friscv_pipeline.sv \
+../../rtl/friscv_rv32i_core.sv \
+../../rtl/friscv_axi_or_tracker.sv \
+../../rtl/friscv_mpu.sv \
+../../rtl/friscv_pmp_region.sv \
+../../rtl/friscv_pulser.sv"
+
+yosys -g -DARTY \
+      -p "scratchpad -set xilinx_dsp.multonly 1" \
+      -p "verilog_defaults -add -I../../rtl" \
+      -p "read -define XLEN=32 -sv -I../../rtl $SRCS " \
+      -p "synth_xilinx -nowidelut -flatten -abc9 -arch xc7 -top friscv_rv32i_core " \
+      $SRCS | tee syn.log
+
+exit