Merge pull request #3379 from chipsalliance/farewell_sfc

Remove SFC
chipsalliance · Jun 14, 2023 · 2a9936d · 2a9936d
2 parents 3ea90ae + 28aa3d3
commit 2a9936d
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diff --git a/.github/workflows/continuous-integration.yml b/.github/workflows/continuous-integration.yml
diff --git a/.github/workflows/mill-ci.yml b/.github/workflows/mill-ci.yml
@@ -41,7 +41,7 @@ jobs:
 
       - name: run riscv-tests
         run: |
-          nix --experimental-features 'nix-command flakes' develop -c mill -i -j 0 "runnable-test[freechips.rocketchip.system.TestHarness,freechips.rocketchip.system.${{ matrix.config }},_,_].run"
+          nix --experimental-features 'nix-command flakes' develop -c mill -i -j 0 "runnable-riscv-test[freechips.rocketchip.system.TestHarness,freechips.rocketchip.system.${{ matrix.config }},_,_].run"
 
   emulator:
     name: emulator
@@ -89,3 +89,27 @@ jobs:
       - name: run riscv-arch-test
         run: |
           nix develop -c mill -i -j 0 "runnable-arch-test[freechips.rocketchip.system.TestHarness,freechips.rocketchip.system.${{ matrix.config }}].run"
+
+  jtag-dtm-test:
+    name: jtag-dtm-test
+    runs-on: ubuntu-latest
+    strategy:
+      matrix:
+        config: ["freechips.rocketchip.system.WithJtagDTMSystem_freechips.rocketchip.system.DefaultConfig", "freechips.rocketchip.system.WithJtagDTMSystem_freechips.rocketchip.system.DefaultRV32Config", "freechips.rocketchip.system.WithJtagDTMSystem_freechips.rocketchip.system.WithDebugSBASystem_freechips.rocketchip.system.DefaultConfig", "freechips.rocketchip.system.WithJtagDTMSystem_freechips.rocketchip.system.WithDebugSBASystem_freechips.rocketchip.system.DefaultRV32Config"]
+    steps:
+      - uses: actions/checkout@v2
+        with:
+          submodules: 'true'
+
+      - name: install nix
+        uses: cachix/install-nix-action@v19
+        with:
+          install_url: https://releases.nixos.org/nix/nix-2.13.3/install
+          nix_path: nixpkgs=channel:nixos-unstable
+
+      - name: Coursier Cache
+        uses: coursier/cache-action@v6
+
+      - name: run jtag-dtm-test
+        run: |
+          nix develop -c mill -i -j 0 "runnable-jtag-dtm-test[freechips.rocketchip.system.TestHarness,${{ matrix.config }},_,_,_].run"
diff --git a/build.sc b/build.sc
@@ -65,15 +65,24 @@ def envByNameOrRiscv(name: String): String = {
   }
 }
 
+/** object to elaborate verilated emulators. */
 object emulator extends mill.Cross[Emulator](
+  // RocketSuiteA
   ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultConfig"),
+  // RocketSuiteB
   ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultBufferlessConfig"),
-  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultRV32Config"),
+  // RocketSuiteC
   ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.TinyConfig"),
-  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultFP16Config"),
-  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.BitManipCryptoConfig"),
-  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.BitManipCrypto32Config"),
-  // Misc
+  // Unittest
+  ("freechips.rocketchip.unittest.TestHarness", "freechips.rocketchip.unittest.AMBAUnitTestConfig"),
+  ("freechips.rocketchip.unittest.TestHarness", "freechips.rocketchip.unittest.TLSimpleUnitTestConfig"),
+  ("freechips.rocketchip.unittest.TestHarness", "freechips.rocketchip.unittest.TLWidthUnitTestConfig"),
+  // DTM
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.WithJtagDTMSystem_freechips.rocketchip.system.WithDebugSBASystem_freechips.rocketchip.system.DefaultConfig"),
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.WithJtagDTMSystem_freechips.rocketchip.system.WithDebugSBASystem_freechips.rocketchip.system.DefaultRV32Config"),
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.WithJtagDTMSystem_freechips.rocketchip.system.DefaultConfig"),
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.WithJtagDTMSystem_freechips.rocketchip.system.DefaultRV32Config"),
+  // Miscellaneous
   ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultSmallConfig"),
   ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DualBankConfig"),
   ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DualChannelConfig"),
@@ -88,6 +97,11 @@ object emulator extends mill.Cross[Emulator](
   ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.MMIOPortOnlyConfig"),
   ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.CloneTileConfig"),
   ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.HypervisorConfig"),
+  // 
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultRV32Config"),
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultFP16Config"),
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.BitManipCryptoConfig"),
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.BitManipCrypto32Config"),
 )
 class Emulator(top: String, config: String) extends Module {
 
@@ -97,10 +111,9 @@ class Emulator(top: String, config: String) extends Module {
         mill.modules.Jvm.javaExe,
         "-jar",
         rocketchip.assembly().path,
-        "freechips.rocketchip.system.Generator",
-        "-td", T.dest.toString,
-        "-T", top,
-        "-C", config,
+        "--dir", T.dest.toString,
+        "--top", top,
+        config.split('_').flatMap(c => Seq("--config", c)),
       ).call()
       PathRef(T.dest)
     }
@@ -204,7 +217,7 @@ class Emulator(top: String, config: String) extends Module {
     def verilatorArgs = T.input {
       Seq(
         // format: off
-        "-Wno-UNOPTTHREADS", "-Wno-STMTDLY", "-Wno-LATCH", "-Wno-WIDTH",
+        "-Wno-UNOPTTHREADS", "-Wno-STMTDLY", "-Wno-LATCH", "-Wno-WIDTH", "--no-timing",
         "--x-assign unique",
         """+define+PRINTF_COND=\$c\(\"verbose\",\"&&\",\"done_reset\"\)""",
         """+define+STOP_COND=\$c\(\"done_reset\"\)""",
@@ -259,7 +272,7 @@ object `riscv-tests` extends Module {
   }
 }
 
-object `runnable-test` extends mill.Cross[RunableTest](
+object `runnable-riscv-test` extends mill.Cross[RiscvTest](
   ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultConfig", "rv64mi-p", "none"),
   ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultConfig", "rv64mi-p-ld", "none"),
   ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultConfig", "rv64mi-p-lh", "none"),
@@ -337,8 +350,9 @@ object `runnable-test` extends mill.Cross[RunableTest](
   ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultFP16Config", "rv64uzfh-p", "none"),
   ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.DefaultFP16Config", "rv64uzfh-v", "none"),
 )
+
 // exclude defaults to "none" instead of "" because it is a file name
-class RunableTest(top: String, config: String, suiteName: String, exclude: String) extends Module {
+class RiscvTest(top: String, config: String, suiteName: String, exclude: String) extends Module {
   def run = T {
     `riscv-tests`.suite(suiteName).binaries().map { bin =>
       val name = bin.path.last
@@ -487,3 +501,48 @@ class ArchTest(top: String, config: String, xlen: String, isa: String) extends M
     }
   }
 }
+
+object `runnable-jtag-dtm-test` extends mill.Cross[JTAGDTMTest](
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.WithJtagDTMSystem_freechips.rocketchip.system.DefaultConfig", "off", "64", "DebugTest"),
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.WithJtagDTMSystem_freechips.rocketchip.system.DefaultConfig", "off", "64", "MemTest64"),
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.WithJtagDTMSystem_freechips.rocketchip.system.DefaultRV32Config", "off", "32", "DebugTest"),
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.WithJtagDTMSystem_freechips.rocketchip.system.DefaultRV32Config", "off", "32", "MemTest64"),
+  // SBA
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.WithJtagDTMSystem_freechips.rocketchip.system.WithDebugSBASystem_freechips.rocketchip.system.DefaultConfig", "on", "64", "MemTest64"),
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.WithJtagDTMSystem_freechips.rocketchip.system.WithDebugSBASystem_freechips.rocketchip.system.DefaultConfig", "on", "64", "MemTest32"),
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.WithJtagDTMSystem_freechips.rocketchip.system.WithDebugSBASystem_freechips.rocketchip.system.DefaultRV32Config", "on", "32", "MemTest64"),
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.WithJtagDTMSystem_freechips.rocketchip.system.WithDebugSBASystem_freechips.rocketchip.system.DefaultRV32Config", "on", "32", "MemTest32"),
+  ("freechips.rocketchip.system.TestHarness", "freechips.rocketchip.system.WithJtagDTMSystem_freechips.rocketchip.system.WithDebugSBASystem_freechips.rocketchip.system.DefaultRV32Config", "on", "32", "MemTest8"),
+)
+
+class JTAGDTMTest(top: String, config: String, sba: String, xlen: String, name: String) extends Module {
+  def run = T {
+    val gdbserver = os.Path(sys.env.get("RISCV_TESTS_ROOT").get) / "debug" / "gdbserver.py"
+    val p = os.proc(
+      gdbserver,
+      "--print-failures",
+      "--print-log-names",
+      s"--sim_cmd=${emulator(top, config).elf().path} +jtag_rbb_enable=1 dummybin",
+      "--server_cmd=openocd",
+      "--gdb=riscv64-none-elf-gdb",
+      s"--${xlen}",
+      s"./scripts/RocketSim${xlen}.py",
+      name,
+    ).call(
+      env = Map(
+          "TERM" -> "", // otherwise readline issues on bracketed-paste
+          "JTAG_DTM_ENABLE_SBA" -> sba,
+        ),
+      stdout = T.dest / s"$name.running.log",
+      mergeErrIntoOut = true,
+      check = false)
+    PathRef(if (p.exitCode != 0) {
+      os.move(T.dest / s"$name.running.log", T.dest / s"$name.failed.log")
+      throw new Exception(s"Test $name failed with exit code ${p.exitCode}")
+      T.dest / s"$name.failed.log"
+    } else {
+      os.move(T.dest / s"$name.running.log", T.dest / s"$name.passed.log")
+      T.dest / s"$name.passed.log"
+    })
+  }
+}
diff --git a/common.sc b/common.sc
@@ -77,7 +77,7 @@ trait CommonRocketChip extends SbtModule with PublishModule {
   ) else Agg.empty[Dep]
 
   override def mainClass = T {
-    Some("freechips.rocketchip.system.Generator")
+    Some("freechips.rocketchip.diplomacy.Main")
   }
 
   override def moduleDeps = Seq(macros) ++ chisel3Module :+ hardfloatModule :+ cdeModule
@@ -90,7 +90,8 @@ trait CommonRocketChip extends SbtModule with PublishModule {
     Agg(
       ivy"${scalaOrganization()}:scala-reflect:${scalaVersion()}",
       ivy"org.json4s::json4s-jackson:4.0.5",
-      ivy"org.scalatest::scalatest:3.2.0"
+      ivy"org.scalatest::scalatest:3.2.0",
+      ivy"com.lihaoyi::mainargs:0.5.0"
     ) ++ chisel3IvyDeps
   }
 

diff --git a/flake.nix b/flake.nix
@@ -22,6 +22,8 @@
           verilator cmake ninja
           python3 python3Packages.bootstrapped-pip
           pkgsCross.riscv64-embedded.buildPackages.gcc
+          pkgsCross.riscv64-embedded.buildPackages.gdb
+          openocd
           circt
 
           spike riscvTests
@@ -41,7 +43,7 @@
               export PYTHONPATH="$PIP_PREFIX/${pkgs.python3.sitePackages}:$PYTHONPATH"
               export PATH="$PIP_PREFIX/bin:$PATH"
               unset SOURCE_DATE_EPOCH
-              pip3 install importlib-metadata typing-extensions riscof==1.25.2
+              pip3 install importlib-metadata typing-extensions riscof==1.25.2 pexpect
             '';
           };
         }

diff --git a/overlay.nix b/overlay.nix
@@ -16,5 +16,12 @@ final: prev: {
       "--prefix=${placeholder "out"}/riscv64-unknown-elf"
     ];
     buildPhase = "make RISCV_PREFIX=riscv64-none-elf-";
+    installPhase = ''
+      runHook preInstall
+      make install
+      mkdir -p $out/debug/
+      cp debug/*.py $out/debug/
+      runHook postInstall
+    '';
   };
 }
diff --git a/src/main/scala/aspects/RenameModulesAspect.scala b/src/main/scala/aspects/RenameModulesAspect.scala