Merge pull request #3378 from chipsalliance/chisel36

fix compile for chisel3.6

common.sc

@@ -4,8 +4,8 @@ import mill.scalalib.publish._
 import coursier.maven.MavenRepository
 
 val defaultVersions = Map(
-  "chisel3" -> "3.6.0-RC2",
-  "chisel3-plugin" -> "3.6.0-RC2"
+  "chisel3" -> "3.6.0",
+  "chisel3-plugin" -> "3.6.0"
 )
 
 def getVersion(dep: String, org: String = "edu.berkeley.cs", cross: Boolean = false) = {

src/main/scala/devices/debug/Debug.scala

@@ -895,7 +895,7 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int, beatBytes: I
     if (nComponents > 1) {
       when (~io.dmactive) {
         selectedHartReg := 0.U
-      }.elsewhen (io.innerCtrl.fire()){
+      }.elsewhen (io.innerCtrl.fire){
         selectedHartReg := io.innerCtrl.bits.hartsel
       }
     }
@@ -905,7 +905,7 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int, beatBytes: I
       val hamaskReg = Reg(Vec(nComponents, Bool()))
       when (~io.dmactive || ~dmAuthenticated) {
         hamaskReg := hamaskZero
-      }.elsewhen (io.innerCtrl.fire()){
+      }.elsewhen (io.innerCtrl.fire){
         hamaskReg := Mux(io.innerCtrl.bits.hasel, io.innerCtrl.bits.hamask, hamaskZero)
       }
       hamaskFull := hamaskReg
@@ -943,7 +943,7 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int, beatBytes: I
 
     when (~io.dmactive || ~dmAuthenticated) {
       hrmaskReg := hrReset
-    }.elsewhen (io.innerCtrl.fire()){
+    }.elsewhen (io.innerCtrl.fire){
       hrmaskReg := io.innerCtrl.bits.hrmask
     }
 
@@ -970,7 +970,7 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int, beatBytes: I
     DMSTATUSRdData.version       := 2.U    // Version 0.13
     io.auth.map(a => DMSTATUSRdData.authbusy := a.dmAuthBusy)
 
-    val resumereq = io.innerCtrl.fire() && io.innerCtrl.bits.resumereq
+    val resumereq = io.innerCtrl.fire && io.innerCtrl.bits.resumereq
 
     when (dmAuthenticated) {
       DMSTATUSRdData.hasresethaltreq := true.B
@@ -1003,7 +1003,7 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int, beatBytes: I
     when(~io.dmactive || ~dmAuthenticated) {
       haveResetBitRegs := 0.U
     }.otherwise {
-      when (io.innerCtrl.fire() && io.innerCtrl.bits.ackhavereset) {
+      when (io.innerCtrl.fire && io.innerCtrl.bits.ackhavereset) {
         haveResetBitRegs := (haveResetBitRegs & (~(hamaskWrSel.asUInt))) | hartIsInResetSync.asUInt 
       }.otherwise {
         haveResetBitRegs := haveResetBitRegs | hartIsInResetSync.asUInt 

src/main/scala/devices/debug/DebugTransport.scala

@@ -143,7 +143,7 @@ class DebugTransportModuleJTAG(debugAddrBits: Int, c: JtagDTMConfig)
   when (io.dmi.req.valid) {
     busyReg := true.B
   }
-  when (io.dmi.resp.fire()) {
+  when (io.dmi.resp.fire) {
     busyReg := false.B
   }
 
@@ -200,7 +200,7 @@ class DebugTransportModuleJTAG(debugAddrBits: Int, c: JtagDTMConfig)
   // Drive Ready Valid Interface
 
   val dmiReqValidCheck = WireInit(false.B)
-  assert(!(dmiReqValidCheck && io.dmi.req.fire()), "Conflicting updates for dmiReqValidReg, should not happen.");
+  assert(!(dmiReqValidCheck && io.dmi.req.fire), "Conflicting updates for dmiReqValidReg, should not happen.");
 
   when (dmiAccessChain.io.update.valid) {
     when (stickyBusyReg) {
@@ -217,7 +217,7 @@ class DebugTransportModuleJTAG(debugAddrBits: Int, c: JtagDTMConfig)
     }
   }
 
-  when (io.dmi.req.fire()) {
+  when (io.dmi.req.fire) {
     dmiReqValidReg := false.B
   }
 

src/main/scala/diplomacy/BundleBridge.scala

@@ -3,8 +3,7 @@
 package freechips.rocketchip.diplomacy
 
 import chisel3._
-import chisel3.experimental.SourceInfo
-import chisel3.experimental.{DataMirror,IO}
+import chisel3.experimental.{DataMirror, SourceInfo}
 import chisel3.experimental.DataMirror.internal.chiselTypeClone
 import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.util.DataToAugmentedData

src/main/scala/diplomacy/Nodes.scala

@@ -3,7 +3,7 @@
 package freechips.rocketchip.diplomacy
 
 import Chisel._
-import chisel3.experimental.IO
+import chisel3.IO
 import chisel3.experimental.SourceInfo
 import org.chipsalliance.cde.config.{Field, Parameters}
 import freechips.rocketchip.util.HeterogeneousBag

src/main/scala/prci/ClockGroupDriver.scala

@@ -2,7 +2,6 @@
 package freechips.rocketchip.prci
 
 import chisel3._
-import chisel3.experimental.IO
 import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.diplomacy.{InModuleBody, ModuleValue, ValName}
 import freechips.rocketchip.util.{RecordMap}

src/main/scala/prci/IOHelper.scala

@@ -3,7 +3,6 @@
 package freechips.rocketchip.prci
 
 import chisel3._
-import chisel3.experimental.IO
 import freechips.rocketchip.diplomacy._
 
 object IOHelper {

src/main/scala/rocket/DCache.scala

@@ -156,13 +156,13 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
       (tl_out.c, true.B)
     }
 
-  val s1_valid = RegNext(io.cpu.req.fire(), false.B)
-  val s1_probe = RegNext(tl_out.b.fire(), false.B)
-  val probe_bits = RegEnable(tl_out.b.bits, tl_out.b.fire()) // TODO has data now :(
+  val s1_valid = RegNext(io.cpu.req.fire, false.B)
+  val s1_probe = RegNext(tl_out.b.fire, false.B)
+  val probe_bits = RegEnable(tl_out.b.bits, tl_out.b.fire) // TODO has data now :(
   val s1_nack = WireDefault(false.B)
   val s1_valid_masked = s1_valid && !io.cpu.s1_kill
   val s1_valid_not_nacked = s1_valid && !s1_nack
-  val s1_tlb_req_valid = RegNext(tlb_port.req.fire(), false.B)
+  val s1_tlb_req_valid = RegNext(tlb_port.req.fire, false.B)
   val s2_tlb_req_valid = RegNext(s1_tlb_req_valid, false.B)
   val s0_clk_en = metaArb.io.out.valid && !metaArb.io.out.bits.write
 
@@ -174,7 +174,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
   val s1_vaddr = Cat(s1_req.idx.getOrElse(s1_req.addr) >> tagLSB, s1_req.addr(tagLSB-1, 0))
 
   val s0_tlb_req = WireInit(tlb_port.req.bits)
-  when (!tlb_port.req.fire()) {
+  when (!tlb_port.req.fire) {
     s0_tlb_req.passthrough := s0_req.phys
     s0_tlb_req.vaddr := s0_req.addr
     s0_tlb_req.size := s0_req.size
@@ -605,7 +605,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
 
   // Set pending bits for outstanding TileLink transaction
   val a_sel = UIntToOH(a_source, maxUncachedInFlight+mmioOffset) >> mmioOffset
-  when (tl_out_a.fire()) {
+  when (tl_out_a.fire) {
     when (s2_uncached) {
       (a_sel.asBools zip (uncachedInFlight zip uncachedReqs)) foreach { case (s, (f, r)) =>
         when (s) {
@@ -648,7 +648,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
   tl_out.d.ready := Mux(grantIsCached, (!d_first || tl_out.e.ready) && canAcceptCachedGrant, true.B)
   val uncachedRespIdxOH = UIntToOH(tl_out.d.bits.source, maxUncachedInFlight+mmioOffset) >> mmioOffset
   uncachedResp := Mux1H(uncachedRespIdxOH, uncachedReqs)
-  when (tl_out.d.fire()) {
+  when (tl_out.d.fire) {
     when (grantIsCached) {
       grantInProgress := true.B
       assert(cached_grant_wait, "A GrantData was unexpected by the dcache.")
@@ -690,7 +690,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
   // Finish TileLink transaction by issuing a GrantAck
   tl_out.e.valid := tl_out.d.valid && d_first && grantIsCached && canAcceptCachedGrant
   tl_out.e.bits := edge.GrantAck(tl_out.d.bits)
-  assert(tl_out.e.fire() === (tl_out.d.fire() && d_first && grantIsCached))
+  assert(tl_out.e.fire === (tl_out.d.fire && d_first && grantIsCached))
 
   // data refill
   // note this ready-valid signaling ignores E-channel backpressure, which
@@ -775,9 +775,9 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
   // release
   val (c_first, c_last, releaseDone, c_count) = edge.count(tl_out_c)
   val releaseRejected = Wire(Bool())
-  val s1_release_data_valid = RegNext(dataArb.io.in(2).fire())
+  val s1_release_data_valid = RegNext(dataArb.io.in(2).fire)
   val s2_release_data_valid = RegNext(s1_release_data_valid && !releaseRejected)
-  releaseRejected := s2_release_data_valid && !tl_out_c.fire()
+  releaseRejected := s2_release_data_valid && !tl_out_c.fire
   val releaseDataBeat = Cat(0.U, c_count) + Mux(releaseRejected, 0.U, s1_release_data_valid + Cat(0.U, s2_release_data_valid))
 
   val nackResponseMessage = edge.ProbeAck(b = probe_bits, reportPermissions = TLPermissions.NtoN)
@@ -853,7 +853,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
       newCoh := voluntaryNewCoh
       releaseWay := s2_victim_or_hit_way
       when (releaseDone) { release_state := s_voluntary_write_meta }
-      when (tl_out_c.fire() && c_first) {
+      when (tl_out_c.fire && c_first) {
         release_ack_wait := true.B
         release_ack_addr := probe_bits.address
       }
@@ -888,7 +888,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
   metaArb.io.in(4).bits.idx := probeIdx(probe_bits)
   metaArb.io.in(4).bits.addr := Cat(io.cpu.req.bits.addr >> untagBits, probe_bits.address(idxMSB, 0))
   metaArb.io.in(4).bits.data := tECC.encode(L1Metadata(tl_out_c.bits.address >> tagLSB, newCoh).asUInt)
-  when (metaArb.io.in(4).fire()) { release_state := s_ready }
+  when (metaArb.io.in(4).fire) { release_state := s_ready }
 
   // cached response
   (io.cpu.resp.bits: Data).waiveAll :<>= (s2_req: Data).waiveAll
@@ -923,7 +923,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
   val s2_uncached_data_word = RegEnable(s1_uncached_data_word, io.cpu.replay_next)
   val doUncachedResp = RegNext(io.cpu.replay_next)
   io.cpu.resp.valid := (s2_valid_hit_pre_data_ecc || doUncachedResp) && !s2_data_error
-  io.cpu.replay_next := tl_out.d.fire() && grantIsUncachedData && !cacheParams.separateUncachedResp.B
+  io.cpu.replay_next := tl_out.d.fire && grantIsUncachedData && !cacheParams.separateUncachedResp.B
   when (doUncachedResp) {
     assert(!s2_valid_hit)
     io.cpu.resp.bits.replay := true.B
@@ -987,7 +987,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
   val flushCounterWrap = flushCounterNext(log2Ceil(nSets)-1, 0)
   ccover(s2_valid_masked && s2_cmd_flush_all && s2_meta_error, "TAG_ECC_ERROR_DURING_FENCE_I", "D$ ECC error in tag array during cache flush")
   ccover(s2_valid_masked && s2_cmd_flush_all && s2_data_error, "DATA_ECC_ERROR_DURING_FENCE_I", "D$ ECC error in data array during cache flush")
-  s1_flush_valid := metaArb.io.in(5).fire() && !s1_flush_valid && !s2_flush_valid_pre_tag_ecc && release_state === s_ready && !release_ack_wait
+  s1_flush_valid := metaArb.io.in(5).fire && !s1_flush_valid && !s2_flush_valid_pre_tag_ecc && release_state === s_ready && !release_ack_wait
   metaArb.io.in(5).valid := flushing && !flushed
   metaArb.io.in(5).bits.write := false.B
   metaArb.io.in(5).bits.idx := flushCounter(idxBits-1, 0)
@@ -1004,7 +1004,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
       }
     }
 
-    when (tl_out_a.fire() && !s2_uncached) { flushed := false.B }
+    when (tl_out_a.fire && !s2_uncached) { flushed := false.B }
     when (flushing) {
       s1_victim_way := flushCounter >> log2Up(nSets)
       when (s2_flush_valid) {
@@ -1052,7 +1052,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
   io.cpu.perf.acquire := edge.done(tl_out_a)
   io.cpu.perf.release := edge.done(tl_out_c)
   io.cpu.perf.grant := tl_out.d.valid && d_last
-  io.cpu.perf.tlbMiss := io.ptw.req.fire()
+  io.cpu.perf.tlbMiss := io.ptw.req.fire
   io.cpu.perf.storeBufferEmptyAfterLoad := !(
     (s1_valid && s1_write) ||
     ((s2_valid && s2_write && !s2_waw_hazard) || pstore1_held) ||
@@ -1076,7 +1076,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
     }
     val near_end_of_refill = if (cacheBlockBytes / beatBytes <= beatsBeforeEnd) tl_out.d.valid else {
       val refill_count = RegInit(0.U((cacheBlockBytes / beatBytes).log2.W))
-      when (tl_out.d.fire() && grantIsRefill) { refill_count := refill_count + 1.U }
+      when (tl_out.d.fire && grantIsRefill) { refill_count := refill_count + 1.U }
       refill_count >= (cacheBlockBytes / beatBytes - beatsBeforeEnd).U
     }
     cached_grant_wait && !near_end_of_refill
@@ -1085,7 +1085,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
   // report errors
   val (data_error, data_error_uncorrectable, data_error_addr) =
     if (usingDataScratchpad) (s2_valid_data_error, s2_data_error_uncorrectable, s2_req.addr) else {
-      (RegNext(tl_out_c.fire() && inWriteback && s2_data_error),
+      (RegNext(tl_out_c.fire && inWriteback && s2_data_error),
         RegNext(s2_data_error_uncorrectable),
         probe_bits.address) // This is stable for a cycle after tl_out_c.fire, so don't need a register
     }
@@ -1102,7 +1102,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
       c.bits := error_addr
       io.errors.uncorrectable.foreach { u => when (u.valid) { c.valid := false.B } }
     }
-    io.errors.bus.valid := tl_out.d.fire() && (tl_out.d.bits.denied || tl_out.d.bits.corrupt)
+    io.errors.bus.valid := tl_out.d.fire && (tl_out.d.bits.denied || tl_out.d.bits.corrupt)
     io.errors.bus.bits := Mux(grantIsCached, s2_req.addr >> idxLSB << idxLSB, 0.U)
 
     ccoverNotScratchpad(io.errors.bus.valid && grantIsCached, "D_ERROR_CACHED", "D$ D-channel error, cached")

src/main/scala/rocket/HellaCache.scala

@@ -327,7 +327,7 @@ class L1MetadataArray[T <: L1Metadata](onReset: () => T)(implicit p: Parameters)
   when (wen) {
     tag_array.write(waddr, VecInit.fill(nWays)(wdata), wmask)
   }
-  io.resp := tag_array.read(io.read.bits.idx, io.read.fire()).map(_.asTypeOf(chiselTypeOf(rstVal)))
+  io.resp := tag_array.read(io.read.bits.idx, io.read.fire).map(_.asTypeOf(chiselTypeOf(rstVal)))
 
   io.read.ready := !wen // so really this could be a 6T RAM
   io.write.ready := !rst

src/main/scala/rocket/ICache.scala

@@ -319,13 +319,13 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
   def scratchpadLine(addr: UInt) = addr(untagBits+log2Ceil(nWays)-1, blockOffBits)
 
   /** scratchpad access valid in stage N*/
-  val s0_slaveValid = tl_in.map(_.a.fire()).getOrElse(false.B)
+  val s0_slaveValid = tl_in.map(_.a.fire).getOrElse(false.B)
   val s1_slaveValid = RegNext(s0_slaveValid, false.B)
   val s2_slaveValid = RegNext(s1_slaveValid, false.B)
   val s3_slaveValid = RegNext(false.B)
 
   /** valid signal for CPU accessing cache in stage 0. */
-  val s0_valid = io.req.fire()
+  val s0_valid = io.req.fire
   /** virtual address from CPU in stage 0. */
   val s0_vaddr = io.req.bits.addr
 
@@ -363,7 +363,7 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
    * */
   val send_hint = RegInit(false.B)
   /** indicate [[tl_out]] is performing a refill. */
-  val refill_fire = tl_out.a.fire() && !send_hint
+  val refill_fire = tl_out.a.fire && !send_hint
   /** register to indicate there is a outstanding hint. */
   val hint_outstanding = RegInit(false.B)
   /** [[io]] access L1 I$ miss. */
@@ -380,14 +380,14 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
   val refill_tag = refill_paddr >> pgUntagBits
   val refill_idx = index(refill_vaddr, refill_paddr)
   /** AccessAckData, is refilling I$, it will block request from CPU. */
-  val refill_one_beat = tl_out.d.fire() && edge_out.hasData(tl_out.d.bits)
+  val refill_one_beat = tl_out.d.fire && edge_out.hasData(tl_out.d.bits)
 
   /** block request from CPU when refill or scratch pad access. */
   io.req.ready := !(refill_one_beat || s0_slaveValid || s3_slaveValid)
   s1_valid := s0_valid
 
   val (_, _, d_done, refill_cnt) = edge_out.count(tl_out.d)
-  /** at last beat of `tl_out.d.fire()`, finish refill. */
+  /** at last beat of `tl_out.d.fire`, finish refill. */
   val refill_done = refill_one_beat && d_done
   /** scratchpad is writing data. block refill. */
   tl_out.d.ready := !s3_slaveValid
@@ -430,7 +430,7 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
     ccover(refillError, "D_CORRUPT", "I$ D-channel corrupt")
   }
   // notify CPU, I$ has corrupt.
-  io.errors.bus.valid := tl_out.d.fire() && (tl_out.d.bits.denied || tl_out.d.bits.corrupt)
+  io.errors.bus.valid := tl_out.d.fire && (tl_out.d.bits.denied || tl_out.d.bits.corrupt)
   io.errors.bus.bits  := (refill_paddr >> blockOffBits) << blockOffBits
 
   /** true indicate this cacheline is valid,
@@ -714,7 +714,7 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
         }
 
         // back pressure is allowed on the [[tl]]
-        // pull up [[respValid]] when [[s2_slaveValid]] until [[tl.d.fire()]]
+        // pull up [[respValid]] when [[s2_slaveValid]] until [[tl.d.fire]]
         respValid := s2_slaveValid || (respValid && !tl.d.ready)
         // if [[s2_full_word_write]] will overwrite data, and [[s2_data_decoded.uncorrectable]] can be ignored.
         val respError = RegEnable(s2_scratchpad_hit && s2_data_decoded.uncorrectable && !s1s2_full_word_write, s2_slaveValid)
@@ -767,7 +767,7 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
       */
     val (crosses_page, next_block) = Split(refill_paddr(pgIdxBits-1, blockOffBits) +& 1.U, pgIdxBits-blockOffBits)
 
-    when (tl_out.a.fire()) {
+    when (tl_out.a.fire) {
       send_hint := !hint_outstanding && io.s2_prefetch && !crosses_page
       when (send_hint) {
         send_hint := false.B
@@ -781,7 +781,7 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
     }
 
     // D channel reply with HintAck.
-    when (tl_out.d.fire() && !refill_one_beat) {
+    when (tl_out.d.fire && !refill_one_beat) {
       hint_outstanding := false.B
     }
 
@@ -795,9 +795,9 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
     }
 
     ccover(send_hint && !tl_out.a.ready, "PREFETCH_A_STALL", "I$ prefetch blocked by A-channel")
-    ccover(refill_valid && (tl_out.d.fire() && !refill_one_beat), "PREFETCH_D_BEFORE_MISS_D", "I$ prefetch resolves before miss")
-    ccover(!refill_valid && (tl_out.d.fire() && !refill_one_beat), "PREFETCH_D_AFTER_MISS_D", "I$ prefetch resolves after miss")
-    ccover(tl_out.a.fire() && hint_outstanding, "PREFETCH_D_AFTER_MISS_A", "I$ prefetch resolves after second miss")
+    ccover(refill_valid && (tl_out.d.fire && !refill_one_beat), "PREFETCH_D_BEFORE_MISS_D", "I$ prefetch resolves before miss")
+    ccover(!refill_valid && (tl_out.d.fire && !refill_one_beat), "PREFETCH_D_AFTER_MISS_D", "I$ prefetch resolves after miss")
+    ccover(tl_out.a.fire && hint_outstanding, "PREFETCH_D_AFTER_MISS_A", "I$ prefetch resolves after second miss")
   }
   // Drive APROT information
   tl_out.a.bits.user.lift(AMBAProt).foreach { x =>

src/main/scala/rocket/Multiplier.scala

@@ -155,10 +155,10 @@ class MulDiv(cfg: MulDivParams, width: Int, nXpr: Int = 32, aluFn: ALUFN = new A
     }
     when (divby0 && !isHi) { neg_out := false.B }
   }
-  when (io.resp.fire() || io.kill) {
+  when (io.resp.fire || io.kill) {
     state := s_ready
   }
-  when (io.req.fire()) {
+  when (io.req.fire) {
     state := Mux(cmdMul, s_mul, Mux(lhs_sign || rhs_sign, s_neg_inputs, s_div))
     isHi := cmdHi
     resHi := false.B