RegSysExSRAMOutputQueues

SRAM output queues configuration file

Register system reference

(Current as of 5 Apr, 2010.)

<nf:module xmlns:nf="http://www.NetFPGA.org/NF2_register_system" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.NetFPGA.org/NF2_register_system NF2_register_system.xsd ">
	<nf:name>output_queues</nf:name>
	<nf:prefix>oq</nf:prefix>
	<nf:location>udp</nf:location>
	<nf:description>SRAM-based output queue using round-robin removal</nf:description>
	<nf:blocksize>4k</nf:blocksize>
	<nf:registers>
		<nf:register_group>
			<nf:name>queue</nf:name>
			<nf:instances>:NUM_OUTPUT_QUEUES</nf:instances>
			<nf:register>
				<nf:name>ctrl</nf:name>
				<nf:description>Control register</nf:description>
				<nf:type>oq_control</nf:type>
			</nf:register>
			<nf:register>
				<nf:name>num_pkt_bytes_stored</nf:name>
				<nf:description>Number of packet bytes stored</nf:description>
				<nf:type>sram_byte_cnt</nf:type>
			</nf:register>
			<nf:register>
				<nf:name>num_overhead_bytes_stored</nf:name>
				<nf:description>Number of overhead (control) bytes stored</nf:description>
				<nf:type>sram_byte_cnt</nf:type>
			</nf:register>
			<nf:register>
				<nf:name>num_pkt_bytes_removed</nf:name>
				<nf:description>Number of packet bytes removed</nf:description>
				<nf:type>sram_byte_cnt</nf:type>
			</nf:register>
			<nf:register>
				<nf:name>num_overhead_bytes_removed</nf:name>
				<nf:description>Number of overhead (control) bytes removed</nf:description>
				<nf:type>sram_byte_cnt</nf:type>
			</nf:register>
			<nf:register>
				<nf:name>num_pkts_stored</nf:name>
				<nf:description>Number of packets stored</nf:description>
				<nf:type>sram_pkt_cnt</nf:type>
			</nf:register>
			<nf:register>
				<nf:name>num_pkts_dropped</nf:name>
				<nf:description>Number of packets dropped</nf:description>
				<nf:type>sram_pkt_cnt</nf:type>
			</nf:register>
			<nf:register>
				<nf:name>num_pkts_removed</nf:name>
				<nf:description>Number of packets removed</nf:description>
				<nf:type>sram_pkt_cnt</nf:type>
			</nf:register>
			<nf:register>
				<nf:name>addr_lo</nf:name>
				<nf:description>Queue low address</nf:description>
				<nf:type>sram_addr</nf:type>
			</nf:register>
			<nf:register>
				<nf:name>addr_hi</nf:name>
				<nf:description>Queue high address</nf:description>
				<nf:type>sram_addr</nf:type>
			</nf:register>
			<nf:register>
				<nf:name>rd_addr</nf:name>
				<nf:description>Queue read address</nf:description>
				<nf:type>sram_addr</nf:type>
			</nf:register>
			<nf:register>
				<nf:name>wr_addr</nf:name>
				<nf:description>Queue write address</nf:description>
				<nf:type>sram_addr</nf:type>
			</nf:register>
			<nf:register>
				<nf:name>num_pkts_in_q</nf:name>
				<nf:description>Number of packets in the queue</nf:description>
				<nf:type>sram_pkt_cnt</nf:type>
			</nf:register>
			<nf:register>
				<nf:name>max_pkts_in_q</nf:name>
				<nf:description>Maximum number of packets allowed in queue</nf:description>
				<nf:type>sram_pkt_cnt</nf:type>
			</nf:register>
			<nf:register>
				<nf:name>num_words_in_q</nf:name>
				<nf:description>Number of words in the queue</nf:description>
				<nf:type>sram_word_cnt</nf:type>
			</nf:register>
			<nf:register>
				<nf:name>num_words_left</nf:name>
				<nf:description>Number of words of space left</nf:description>
				<nf:type>sram_word_cnt</nf:type>
			</nf:register>
			<nf:register>
				<nf:name>full_thresh</nf:name>
				<nf:description>Full threshold (minimum number of words)</nf:description>
				<nf:type>sram_word_cnt</nf:type>
			</nf:register>
		</nf:register_group>
	</nf:registers>
	<nf:constants>
		
		<nf:constant>
			<nf:name>:NUM_OUTPUT_QUEUES</nf:name>
			<nf:value>8</nf:value>
		</nf:constant>
		<nf:constant>
			<nf:name>DEFAULT_MAX_PKTS</nf:name>
			<nf:width>SRAM_PKT_CNT_WIDTH</nf:width>
			<nf:value>0xffffffff</nf:value>
		</nf:constant>
		<nf:constant>
			<nf:name>SRAM_PKT_CNT_WIDTH</nf:name>
			<nf:value>:SRAM_ADDR_WIDTH</nf:value>
		</nf:constant>
		<nf:constant>
			<nf:name>SRAM_WORD_CNT_WIDTH</nf:name>
			<nf:value>:SRAM_ADDR_WIDTH</nf:value>
		</nf:constant>
		<nf:constant>
			<nf:name>SRAM_BYTE_CNT_WIDTH</nf:name>
			<nf:value>:SRAM_ADDR_WIDTH</nf:value>
		</nf:constant>
		<nf:constant>
			<nf:name>ENABLE_SEND_BIT_NUM</nf:name>
			<nf:value>0</nf:value>
		</nf:constant>
		<nf:constant>
			<nf:name>INITIALIZE_OQ_BIT_NUM</nf:name>
			<nf:value>1</nf:value>
		</nf:constant>
	</nf:constants>
	<nf:types>
		<nf:type xsi:type="nf:SimpleType">
			<nf:name>sram_pkt_cnt</nf:name>
			<nf:width>SRAM_PKT_CNT_WIDTH</nf:width>
		</nf:type>
		<nf:type xsi:type="nf:SimpleType">
			<nf:name>sram_word_cnt</nf:name>
			<nf:width>SRAM_WORD_CNT_WIDTH</nf:width>
		</nf:type>
		<nf:type xsi:type="nf:SimpleType">
			<nf:name>sram_byte_cnt</nf:name>
			<nf:width>SRAM_BYTE_CNT_WIDTH</nf:width>
		</nf:type>
		<nf:type xsi:type="nf:SimpleType">
			<nf:name>sram_addr</nf:name>
			<nf:width>:SRAM_ADDR_WIDTH</nf:width>
		</nf:type>
		<nf:type xsi:type="nf:SimpleType">
			<nf:name>oq_control</nf:name>
			<nf:width>2</nf:width>
			<nf:bitmask>
				<nf:name>enable_send</nf:name>
				<nf:pos>0</nf:pos>
			</nf:bitmask>
			<nf:bitmask>
				<nf:name>initialize_oq</nf:name>
				<nf:pos>1</nf:pos>
			</nf:bitmask>
		</nf:type>
	</nf:types>
</nf:module>