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DRAMQueueTest
This project makes use of 64MBytes DDR2 DRAM on the NetFPGA card for packet buffering. The design has 1 DRAM queue before the original SRAM output queues to demonstrate the ability of driving onboard DRAM for packet buffering.
- Status :
- Version :
- Author :
- NetFPGA source (required only for project source release) :
The DRAM queue test is released with NetFPGA 2.0 Beta Base package.
The regression tests verify the functionality of the dram_queue_test. In order to run the tests, you need to have the machine connected for the regression tests as stated in the Run Regression Tests section of the Guide.
After connecting the cables. Run the following command to run the regression tests.
nf2_regress_test.pl --project dram_queue_test
Most of the regression tests of the project are the same to the reference router. This is by design because we want to demonstrate that the DDR2 DRAM has the same (actually even higher) ability of packet buffering. Follow the Beta Release Regression Tests for details of those tests.
Moreover, each project has some extra tests that verifies the counters of DDR2 DRAM counters. They are described as follows.
- Project :
- Name :
- Description:
- Turn off the shortcut
- Send a number of packets, which go through DDR2 DRAM
- Turn on the shortcut, allowing those words stored in tail cache going out
- Verify the counters: Input words, Output words, Shortcut words, DRAM write words, DRAM read words
- Location
projects/dram_queue_test/regress/test_dram_queue
- Output
SUCCESS!
Both projects are based on DDR2 Block Data Read Write module. This module provides a block read/write interface to user datapath pipeline.
The block read/write module takes 2034 bytes in each read/write. That requires the user datapath side to buffer the packets until the data exceeds this threshold. We implemented the buffer with Block RAM (BRAM).
In this project, we implemented a "DRAM queue" that has input/output on user datapath side, and a DRAM Block Read/Write interface on memory side.
The DRAM queue is located before SRAM output queues.
There are two BRAM caches: input FIFO and output FIFO in one queue. Packets go into the input FIFO and are buffered there. When the data in this fifo exceeds 2034 bytes, the content of BRAM FIFO is transferred to DDR2 DRAM. Similarly, when output FIFO has room more than 2034 bytes, the content in DDR2 DRAM is transferred to output BRAM FIFO and finally out of DRAM queue.
Notice that if the content in input FIFO is less than the threshold (2034 Bytes), packets will stay in the FIFO forever. To avoid this, we have a shortcut path connecting two FIFOs. Only when output FIFO cannot handle the incoming packets from input FIFO, contents in input FIFO will be transferred to DDR2 DRAM.
To meet the different data width between user data path (72bit) and DDR2 Block Read/Write (144bit), FIFOs has different width on the input and output. Input FIFO has 72bit input and 144bit output. Output FIFO has 144bit input and 72bit output.
To avoid the last word of odd-word (72bit word) packet hangs on the input FIFO (144bit output), those packets will be appended an extra dummy word before put into the input FIFO. The dummy word will be removed when the whole packet passes DRAM queue.
- XAPP549 - DDR2 SDRAM Memory Interface for Virtex-II Pro FPGAs - Xilinx Application Note for implementing DDR2 memory interfaces
- Xilinx Memory Solutions - Information about interfacing with various memory types. Includes a link to the Memory Interface Generator (MIG User Guide inside .ZIP file)