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drivers: gpio: xlnx_ps: switch driver over to DEVICE_MMIO mapping #78255

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drivers: gpio: xlnx_ps: switch driver over to DEVICE_MMIO mapping #78255

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977ce26
drivers: gpio: xlnx_ps: switch driver over to DEVICE_MMIO mapping
ibirnbaum Sep 10, 2024
e60678d
soc: xlnx: zynq7000: remove PS GPIO controller's static memory mapping
ibirnbaum Sep 10, 2024
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28 changes: 24 additions & 4 deletions drivers/gpio/gpio_xlnx_ps.c
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Original file line number Diff line number Diff line change
Expand Up @@ -20,6 +20,9 @@

#define DT_DRV_COMPAT xlnx_ps_gpio

#define DEV_CFG(_dev) ((const struct gpio_xlnx_ps_dev_cfg *)(_dev)->config)
#define DEV_DATA(_dev) ((struct gpio_xlnx_ps_dev_data *const)(_dev)->data)

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drivers/gpio/gpio_xlnx_ps.c:24 
-#define DEV_CFG(_dev) ((const struct gpio_xlnx_ps_dev_cfg *)(_dev)->config)
+#define DEV_CFG(_dev)  ((const struct gpio_xlnx_ps_dev_cfg *)(_dev)->config)

/*
* An API is required for this driver, but as no pin access is provided at
* this level, use the default API contents provided by the driver subsystem.
Expand All @@ -41,7 +44,22 @@
*/
static int gpio_xlnx_ps_init(const struct device *dev)
{
const struct gpio_xlnx_ps_dev_cfg *dev_conf = dev->config;
const struct gpio_xlnx_ps_dev_cfg *dev_conf = DEV_CFG(dev);
struct gpio_xlnx_ps_dev_data *dev_data = DEV_DATA(dev);
uint32_t bank;

/* Perform the actual memory map operation in the parent device */
DEVICE_MMIO_NAMED_MAP(dev, reg_base, K_MEM_CACHE_NONE);
dev_data->base = DEVICE_MMIO_NAMED_GET(dev, reg_base);
__ASSERT(dev_data->base != 0, "%s map register space failed", dev->name);

/* Propagate the virtual base address to the bank devices */
for (bank = 0; bank < dev_conf->num_banks; bank++) {
struct gpio_xlnx_ps_bank_dev_data *bank_data =
dev_conf->bank_devices[bank]->data;
__ASSERT(bank_data != NULL, "%s bank %u data unresolved", dev->name, bank);

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drivers/gpio/gpio_xlnx_ps.c:60 
-		struct gpio_xlnx_ps_bank_dev_data *bank_data =
-			dev_conf->bank_devices[bank]->data;
+		struct gpio_xlnx_ps_bank_dev_data *bank_data = dev_conf->bank_devices[bank]->data;
bank_data->base = dev_data->base;
}

/* Initialize the device's interrupt */
dev_conf->config_func(dev);
Expand All @@ -63,7 +81,7 @@
*/
static void gpio_xlnx_ps_isr(const struct device *dev)
{
const struct gpio_xlnx_ps_dev_cfg *dev_conf = dev->config;
const struct gpio_xlnx_ps_dev_cfg *dev_conf = DEV_CFG(dev);

const struct gpio_driver_api *api;
struct gpio_xlnx_ps_bank_dev_data *bank_data;
Expand Down Expand Up @@ -102,16 +120,18 @@

/* Device config & run-time data struct creation macros */
#define GPIO_XLNX_PS_DEV_DATA(idx)\
static struct gpio_xlnx_ps_dev_data gpio_xlnx_ps##idx##_data;
static struct gpio_xlnx_ps_dev_data gpio_xlnx_ps##idx##_data = {\
.base = 0x0,\
};

#define GPIO_XLNX_PS_DEV_CONFIG(idx)\
static const struct gpio_xlnx_ps_dev_cfg gpio_xlnx_ps##idx##_cfg = {\
.base_addr = DT_INST_REG_ADDR(idx),\
DEVICE_MMIO_NAMED_ROM_INIT(reg_base, DT_DRV_INST(idx)),\
.bank_devices = gpio_xlnx_ps##idx##_banks,\
.num_banks = ARRAY_SIZE(gpio_xlnx_ps##idx##_banks),\
.config_func = gpio_xlnx_ps##idx##_irq_config\
};

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drivers/gpio/gpio_xlnx_ps.c:134 
-#define GPIO_XLNX_PS_DEV_DATA(idx)\
-static struct gpio_xlnx_ps_dev_data gpio_xlnx_ps##idx##_data = {\
-	.base = 0x0,\
-};
+#define GPIO_XLNX_PS_DEV_DATA(idx)                                                                 \
+	static struct gpio_xlnx_ps_dev_data gpio_xlnx_ps##idx##_data = {                           \
+		.base = 0x0,                                                                       \
+	};
 
-#define GPIO_XLNX_PS_DEV_CONFIG(idx)\
-static const struct gpio_xlnx_ps_dev_cfg gpio_xlnx_ps##idx##_cfg = {\
-	DEVICE_MMIO_NAMED_ROM_INIT(reg_base, DT_DRV_INST(idx)),\
-	.bank_devices = gpio_xlnx_ps##idx##_banks,\
-	.num_banks = ARRAY_SIZE(gpio_xlnx_ps##idx##_banks),\
-	.config_func = gpio_xlnx_ps##idx##_irq_config\
-};
+#define GPIO_XLNX_PS_DEV_CONFIG(idx)                                                               \
+	static const struct gpio_xlnx_ps_dev_cfg gpio_xlnx_ps##idx##_cfg = {                       \
+		DEVICE_MMIO_NAMED_ROM_INIT(reg_base, DT_DRV_INST(idx)),                            \
+		.bank_devices = gpio_xlnx_ps##idx##_banks,                                         \
+		.num_banks = ARRAY_SIZE(gpio_xlnx_ps##idx##_banks),                                \
+		.config_func = gpio_xlnx_ps##idx##_irq_config};
/*
* Macro used to generate each parent controller device's IRQ attach
* function.
Expand Down
6 changes: 5 additions & 1 deletion drivers/gpio/gpio_xlnx_ps.h
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Original file line number Diff line number Diff line change
Expand Up @@ -23,6 +23,9 @@ typedef void (*gpio_xlnx_ps_config_irq_t)(const struct device *dev);
*/
struct gpio_xlnx_ps_dev_data {
struct gpio_driver_data common;

DEVICE_MMIO_NAMED_RAM(reg_base);
mem_addr_t base;
};

/**
Expand All @@ -36,7 +39,8 @@ struct gpio_xlnx_ps_dev_data {
struct gpio_xlnx_ps_dev_cfg {
struct gpio_driver_config common;

uint32_t base_addr;
DEVICE_MMIO_NAMED_ROM(reg_base);

const struct device *const *bank_devices;
uint32_t num_banks;
gpio_xlnx_ps_config_irq_t config_func;
Expand Down
43 changes: 31 additions & 12 deletions drivers/gpio/gpio_xlnx_ps_bank.c
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Original file line number Diff line number Diff line change
Expand Up @@ -21,6 +21,9 @@

#define DT_DRV_COMPAT xlnx_ps_gpio_bank

#define DEV_CFG(_dev) ((const struct gpio_xlnx_ps_bank_dev_cfg *)(_dev)->config)
#define DEV_DATA(_dev) ((struct gpio_xlnx_ps_bank_dev_data *const)(_dev)->data)

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drivers/gpio/gpio_xlnx_ps_bank.c:25 
-#define DEV_CFG(_dev) ((const struct gpio_xlnx_ps_bank_dev_cfg *)(_dev)->config)
+#define DEV_CFG(_dev)  ((const struct gpio_xlnx_ps_bank_dev_cfg *)(_dev)->config)

/**
* @brief GPIO bank pin configuration function
*
Expand All @@ -47,7 +50,8 @@
gpio_pin_t pin,
gpio_flags_t flags)
{
const struct gpio_xlnx_ps_bank_dev_cfg *dev_conf = dev->config;
const struct gpio_xlnx_ps_bank_dev_cfg *dev_conf = DEV_CFG(dev);
struct gpio_xlnx_ps_bank_dev_data *dev_data = DEV_DATA(dev);
uint32_t pin_mask = BIT(pin);
uint32_t bank_data;
uint32_t dirm_data;
Expand Down Expand Up @@ -127,7 +131,8 @@
static int gpio_xlnx_ps_bank_get(const struct device *dev,
gpio_port_value_t *value)
{
const struct gpio_xlnx_ps_bank_dev_cfg *dev_conf = dev->config;
const struct gpio_xlnx_ps_bank_dev_cfg *dev_conf = DEV_CFG(dev);
struct gpio_xlnx_ps_bank_dev_data *dev_data = DEV_DATA(dev);

*value = sys_read32(GPIO_XLNX_PS_BANK_DATA_REG);
return 0;
Expand Down Expand Up @@ -159,7 +164,8 @@
gpio_port_pins_t mask,
gpio_port_value_t value)
{
const struct gpio_xlnx_ps_bank_dev_cfg *dev_conf = dev->config;
const struct gpio_xlnx_ps_bank_dev_cfg *dev_conf = DEV_CFG(dev);
struct gpio_xlnx_ps_bank_dev_data *dev_data = DEV_DATA(dev);
uint32_t bank_data;

bank_data = sys_read32(GPIO_XLNX_PS_BANK_DATA_REG);
Expand Down Expand Up @@ -187,7 +193,8 @@
static int gpio_xlnx_ps_bank_set_bits(const struct device *dev,
gpio_port_pins_t pins)
{
const struct gpio_xlnx_ps_bank_dev_cfg *dev_conf = dev->config;
const struct gpio_xlnx_ps_bank_dev_cfg *dev_conf = DEV_CFG(dev);
struct gpio_xlnx_ps_bank_dev_data *dev_data = DEV_DATA(dev);
uint32_t bank_data;

bank_data = sys_read32(GPIO_XLNX_PS_BANK_DATA_REG);
Expand Down Expand Up @@ -215,7 +222,8 @@
static int gpio_xlnx_ps_bank_clear_bits(const struct device *dev,
gpio_port_pins_t pins)
{
const struct gpio_xlnx_ps_bank_dev_cfg *dev_conf = dev->config;
const struct gpio_xlnx_ps_bank_dev_cfg *dev_conf = DEV_CFG(dev);
struct gpio_xlnx_ps_bank_dev_data *dev_data = DEV_DATA(dev);
uint32_t bank_data;

bank_data = sys_read32(GPIO_XLNX_PS_BANK_DATA_REG);
Expand Down Expand Up @@ -243,7 +251,8 @@
static int gpio_xlnx_ps_bank_toggle_bits(const struct device *dev,
gpio_port_pins_t pins)
{
const struct gpio_xlnx_ps_bank_dev_cfg *dev_conf = dev->config;
const struct gpio_xlnx_ps_bank_dev_cfg *dev_conf = DEV_CFG(dev);
struct gpio_xlnx_ps_bank_dev_data *dev_data = DEV_DATA(dev);
uint32_t bank_data;

bank_data = sys_read32(GPIO_XLNX_PS_BANK_DATA_REG);
Expand Down Expand Up @@ -282,7 +291,8 @@
enum gpio_int_mode mode,
enum gpio_int_trig trig)
{
const struct gpio_xlnx_ps_bank_dev_cfg *dev_conf = dev->config;
const struct gpio_xlnx_ps_bank_dev_cfg *dev_conf = DEV_CFG(dev);
struct gpio_xlnx_ps_bank_dev_data *dev_data = DEV_DATA(dev);
uint32_t pin_mask = BIT(pin);
uint32_t int_type_data;
uint32_t int_polarity_data;
Expand Down Expand Up @@ -358,7 +368,8 @@
*/
static uint32_t gpio_xlnx_ps_bank_get_int_status(const struct device *dev)
{
const struct gpio_xlnx_ps_bank_dev_cfg *dev_conf = dev->config;
const struct gpio_xlnx_ps_bank_dev_cfg *dev_conf = DEV_CFG(dev);
struct gpio_xlnx_ps_bank_dev_data *dev_data = DEV_DATA(dev);
uint32_t int_status;

int_status = sys_read32(GPIO_XLNX_PS_BANK_INT_STAT_REG);
Expand Down Expand Up @@ -387,7 +398,7 @@
struct gpio_callback *callback,
bool set)
{
struct gpio_xlnx_ps_bank_dev_data *dev_data = dev->data;
struct gpio_xlnx_ps_bank_dev_data *dev_data = DEV_DATA(dev);

return gpio_manage_callback(&dev_data->callbacks, callback, set);
}
Expand Down Expand Up @@ -419,7 +430,14 @@
*/
static int gpio_xlnx_ps_bank_init(const struct device *dev)
{
const struct gpio_xlnx_ps_bank_dev_cfg *dev_conf = dev->config;
const struct gpio_xlnx_ps_bank_dev_cfg *dev_conf = DEV_CFG(dev);
struct gpio_xlnx_ps_bank_dev_data *dev_data = DEV_DATA(dev);

__ASSERT(dev_data->base != 0, "%s mapped base address missing", dev->name);
if (dev_data->base == 0) {
LOG_ERR("%s mapped base address missing", dev->name);
return -EIO;
}

sys_write32(~0x0, GPIO_XLNX_PS_BANK_INT_DIS_REG); /* Disable all interrupts */
sys_write32(~0x0, GPIO_XLNX_PS_BANK_INT_STAT_REG); /* Clear all interrupts */
Expand All @@ -436,13 +454,14 @@
.common = {\
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(idx),\
},\
.base_addr = DT_REG_ADDR(DT_PARENT(DT_INST(idx, DT_DRV_COMPAT))),\
.bank_index = idx,\
};\
static struct gpio_xlnx_ps_bank_dev_data gpio_xlnx_ps_bank##idx##_data;\
static struct gpio_xlnx_ps_bank_dev_data gpio_xlnx_ps_bank##idx##_data = {\
.base = 0,\
};\
DEVICE_DT_INST_DEFINE(idx, gpio_xlnx_ps_bank_init, NULL,\
&gpio_xlnx_ps_bank##idx##_data, &gpio_xlnx_ps_bank##idx##_cfg,\
PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY, &gpio_xlnx_ps_bank_apis);

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drivers/gpio/gpio_xlnx_ps_bank.c:465 
-#define GPIO_XLNX_PS_BANK_INIT(idx)\
-static const struct gpio_xlnx_ps_bank_dev_cfg gpio_xlnx_ps_bank##idx##_cfg = {\
-	.common = {\
-		.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(idx),\
-	},\
-	.bank_index = idx,\
-};\
-static struct gpio_xlnx_ps_bank_dev_data gpio_xlnx_ps_bank##idx##_data = {\
-	.base = 0,\
-};\
-DEVICE_DT_INST_DEFINE(idx, gpio_xlnx_ps_bank_init, NULL,\
-	&gpio_xlnx_ps_bank##idx##_data, &gpio_xlnx_ps_bank##idx##_cfg,\
-	PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY, &gpio_xlnx_ps_bank_apis);
+#define GPIO_XLNX_PS_BANK_INIT(idx)                                                                \
+	static const struct gpio_xlnx_ps_bank_dev_cfg gpio_xlnx_ps_bank##idx##_cfg = {             \
+		.common =                                                                          \
+			{                                                                          \
+				.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(idx),             \
+			},                                                                         \
+		.bank_index = idx,                                                                 \
+	};                                                                                         \
+	static struct gpio_xlnx_ps_bank_dev_data gpio_xlnx_ps_bank##idx##_data = {                 \
+		.base = 0,                                                                         \
+	};                                                                                         \
+	DEVICE_DT_INST_DEFINE(idx, gpio_xlnx_ps_bank_init, NULL, &gpio_xlnx_ps_bank##idx##_data,   \
+			      &gpio_xlnx_ps_bank##idx##_cfg, PRE_KERNEL_1,                         \
+			      CONFIG_GPIO_INIT_PRIORITY, &gpio_xlnx_ps_bank_apis);
/* Register & initialize all MIO / EMIO GPIO banks specified in the device tree. */
DT_INST_FOREACH_STATUS_OKAY(GPIO_XLNX_PS_BANK_INIT);
29 changes: 14 additions & 15 deletions drivers/gpio/gpio_xlnx_ps_bank.h
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Original file line number Diff line number Diff line change
Expand Up @@ -14,33 +14,33 @@
* Register address calculation macros
* Register address offsets: comp. Zynq-7000 TRM, ug585, chap. B.19
*/
#define GPIO_XLNX_PS_BANK_MASK_DATA_LSW_REG (dev_conf->base_addr\
#define GPIO_XLNX_PS_BANK_MASK_DATA_LSW_REG (dev_data->base\
+ ((uint32_t)dev_conf->bank_index * 0x8))
#define GPIO_XLNX_PS_BANK_MASK_DATA_MSW_REG ((dev_conf->base_addr + 0x04)\
#define GPIO_XLNX_PS_BANK_MASK_DATA_MSW_REG ((dev_data->base + 0x04)\
+ ((uint32_t)dev_conf->bank_index * 0x8))
#define GPIO_XLNX_PS_BANK_DATA_REG ((dev_conf->base_addr + 0x40)\
#define GPIO_XLNX_PS_BANK_DATA_REG ((dev_data->base + 0x40)\
+ ((uint32_t)dev_conf->bank_index * 0x4))
#define GPIO_XLNX_PS_BANK_DATA_RO_REG ((dev_conf->base_addr + 0x60)\
#define GPIO_XLNX_PS_BANK_DATA_RO_REG ((dev_data->base + 0x60)\
+ ((uint32_t)dev_conf->bank_index * 0x4))
#define GPIO_XLNX_PS_BANK_DIRM_REG ((dev_conf->base_addr + 0x204)\
#define GPIO_XLNX_PS_BANK_DIRM_REG ((dev_data->base + 0x204)\
+ ((uint32_t)dev_conf->bank_index * 0x40))
#define GPIO_XLNX_PS_BANK_OEN_REG ((dev_conf->base_addr + 0x208)\
#define GPIO_XLNX_PS_BANK_OEN_REG ((dev_data->base + 0x208)\
+ ((uint32_t)dev_conf->bank_index * 0x40))
#define GPIO_XLNX_PS_BANK_INT_MASK_REG ((dev_conf->base_addr + 0x20C)\
#define GPIO_XLNX_PS_BANK_INT_MASK_REG ((dev_data->base + 0x20C)\
+ ((uint32_t)dev_conf->bank_index * 0x40))
#define GPIO_XLNX_PS_BANK_INT_EN_REG ((dev_conf->base_addr + 0x210)\
#define GPIO_XLNX_PS_BANK_INT_EN_REG ((dev_data->base + 0x210)\
+ ((uint32_t)dev_conf->bank_index * 0x40))
#define GPIO_XLNX_PS_BANK_INT_DIS_REG ((dev_conf->base_addr + 0x214)\
#define GPIO_XLNX_PS_BANK_INT_DIS_REG ((dev_data->base + 0x214)\
+ ((uint32_t)dev_conf->bank_index * 0x40))
#define GPIO_XLNX_PS_BANK_INT_STAT_REG ((dev_conf->base_addr + 0x218)\
#define GPIO_XLNX_PS_BANK_INT_STAT_REG ((dev_data->base + 0x218)\
+ ((uint32_t)dev_conf->bank_index * 0x40))
#define GPIO_XLNX_PS_BANK_INT_TYPE_REG ((dev_conf->base_addr + 0x21C)\
#define GPIO_XLNX_PS_BANK_INT_TYPE_REG ((dev_data->base + 0x21C)\
+ ((uint32_t)dev_conf->bank_index * 0x40))
#define GPIO_XLNX_PS_BANK_INT_POLARITY_REG ((dev_conf->base_addr + 0x220)\
#define GPIO_XLNX_PS_BANK_INT_POLARITY_REG ((dev_data->base + 0x220)\
+ ((uint32_t)dev_conf->bank_index * 0x40))
#define GPIO_XLNX_PS_BANK_INT_ANY_REG ((dev_conf->base_addr + 0x224)\
#define GPIO_XLNX_PS_BANK_INT_ANY_REG ((dev_data->base + 0x224)\
+ ((uint32_t)dev_conf->bank_index * 0x40))

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drivers/gpio/gpio_xlnx_ps_bank.h:43 
-#define GPIO_XLNX_PS_BANK_MASK_DATA_LSW_REG (dev_data->base\
-	+ ((uint32_t)dev_conf->bank_index * 0x8))
-#define GPIO_XLNX_PS_BANK_MASK_DATA_MSW_REG ((dev_data->base + 0x04)\
-	+ ((uint32_t)dev_conf->bank_index * 0x8))
-#define GPIO_XLNX_PS_BANK_DATA_REG          ((dev_data->base + 0x40)\
-	+ ((uint32_t)dev_conf->bank_index * 0x4))
-#define GPIO_XLNX_PS_BANK_DATA_RO_REG       ((dev_data->base + 0x60)\
-	+ ((uint32_t)dev_conf->bank_index * 0x4))
-#define GPIO_XLNX_PS_BANK_DIRM_REG          ((dev_data->base + 0x204)\
-	+ ((uint32_t)dev_conf->bank_index * 0x40))
-#define GPIO_XLNX_PS_BANK_OEN_REG           ((dev_data->base + 0x208)\
-	+ ((uint32_t)dev_conf->bank_index * 0x40))
-#define GPIO_XLNX_PS_BANK_INT_MASK_REG      ((dev_data->base + 0x20C)\
-	+ ((uint32_t)dev_conf->bank_index * 0x40))
-#define GPIO_XLNX_PS_BANK_INT_EN_REG        ((dev_data->base + 0x210)\
-	+ ((uint32_t)dev_conf->bank_index * 0x40))
-#define GPIO_XLNX_PS_BANK_INT_DIS_REG       ((dev_data->base + 0x214)\
-	+ ((uint32_t)dev_conf->bank_index * 0x40))
-#define GPIO_XLNX_PS_BANK_INT_STAT_REG      ((dev_data->base + 0x218)\
-	+ ((uint32_t)dev_conf->bank_index * 0x40))
-#define GPIO_XLNX_PS_BANK_INT_TYPE_REG      ((dev_data->base + 0x21C)\
-	+ ((uint32_t)dev_conf->bank_index * 0x40))
-#define GPIO_XLNX_PS_BANK_INT_POLARITY_REG  ((dev_data->base + 0x220)\
-	+ ((uint32_t)dev_conf->bank_index * 0x40))
-#define GPIO_XLNX_PS_BANK_INT_ANY_REG       ((dev_data->base + 0x224)\
-	+ ((uint32_t)dev_conf->bank_index * 0x40))
+#define GPIO_XLNX_PS_BANK_MASK_DATA_LSW_REG                                                        \
+	(dev_data->base + ((uint32_t)dev_conf->bank_index * 0x8))
+#define GPIO_XLNX_PS_BANK_MASK_DATA_MSW_REG                                                        \
+	((dev_data->base + 0x04) + ((uint32_t)dev_conf->bank_index * 0x8))
+#define GPIO_XLNX_PS_BANK_DATA_REG                                                                 \
+	((dev_data->base + 0x40) + ((uint32_t)dev_conf->bank_index * 0x4))
+#define GPIO_XLNX_PS_BANK_DATA_RO_REG                                                              \
+	((dev_data->base + 0x60) + ((uint32_t)dev_conf->bank_index * 0x4))
+#define GPIO_XLNX_PS_BANK_DIRM_REG                                                                 \
+	((dev_data->base + 0x204) + ((uint32_t)dev_conf->bank_index * 0x40))
+#define GPIO_XLNX_PS_BANK_OEN_REG                                                                  \
+	((dev_data->base + 0x208) + ((uint32_t)dev_conf->bank_index * 0x40))
+#define GPIO_XLNX_PS_BANK_INT_MASK_REG                                                             \
+	((dev_data->base + 0x20C) + ((uint32_t)dev_conf->bank_index * 0x40))
+#define GPIO_XLNX_PS_BANK_INT_EN_REG                                                               \
+	((dev_data->base + 0x210) + ((uint32_t)dev_conf->bank_index * 0x40))
+#define GPIO_XLNX_PS_BANK_INT_DIS_REG                                                              \
+	((dev_data->base + 0x214) + ((uint32_t)dev_conf->bank_index * 0x40))
+#define GPIO_XLNX_PS_BANK_INT_STAT_REG                                                             \
+	((dev_data->base + 0x218) + ((uint32_t)dev_conf->bank_index * 0x40))
+#define GPIO_XLNX_PS_BANK_INT_TYPE_REG                                                             \
+	((dev_data->base + 0x21C) + ((uint32_t)dev_conf->bank_index * 0x40))
+#define GPIO_XLNX_PS_BANK_INT_POLARITY_REG                                                         \
+	((dev_data->base + 0x220) + ((uint32_t)dev_conf->bank_index * 0x40))
+#define GPIO_XLNX_PS_BANK_INT_ANY_REG                                                              \
+	((dev_data->base + 0x224) + ((uint32_t)dev_conf->bank_index * 0x40))
/**
* @brief Run-time modifiable device data structure.
*
Expand All @@ -51,6 +51,7 @@
*/
struct gpio_xlnx_ps_bank_dev_data {
struct gpio_driver_data common;
mem_addr_t base;
sys_slist_t callbacks;
};

Expand All @@ -64,8 +65,6 @@
*/
struct gpio_xlnx_ps_bank_dev_cfg {
struct gpio_driver_config common;

uint32_t base_addr;
uint8_t bank_index;
};

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8 changes: 0 additions & 8 deletions soc/xlnx/zynq7000/xc7zxxx/soc.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -52,14 +52,6 @@ static const struct arm_mmu_region mmu_regions[] = {
MT_DEVICE | MATTR_SHARED | MPERM_R | MPERM_W),
#endif

/* GPIO controller */
#if DT_NODE_HAS_STATUS(DT_NODELABEL(psgpio), okay)
MMU_REGION_FLAT_ENTRY("psgpio",
DT_REG_ADDR(DT_NODELABEL(psgpio)),
DT_REG_SIZE(DT_NODELABEL(psgpio)),
MT_DEVICE | MATTR_SHARED | MPERM_R | MPERM_W),
#endif

DT_FOREACH_STATUS_OKAY(xlnx_xps_gpio_1_00_a, AXI_GPIO_MMU_ENTRY)

};
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8 changes: 0 additions & 8 deletions soc/xlnx/zynq7000/xc7zxxxs/soc.c
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Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -52,14 +52,6 @@ static const struct arm_mmu_region mmu_regions[] = {
MT_DEVICE | MATTR_SHARED | MPERM_R | MPERM_W),
#endif

/* GPIO controller */
#if DT_NODE_HAS_STATUS(DT_NODELABEL(psgpio), okay)
MMU_REGION_FLAT_ENTRY("psgpio",
DT_REG_ADDR(DT_NODELABEL(psgpio)),
DT_REG_SIZE(DT_NODELABEL(psgpio)),
MT_DEVICE | MATTR_SHARED | MPERM_R | MPERM_W),
#endif

DT_FOREACH_STATUS_OKAY(xlnx_xps_gpio_1_00_a, AXI_GPIO_MMU_ENTRY)

};
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