drivers: gpio: xlnx_ps: switch driver over to DEVICE_MMIO mapping #150607
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1 error, 1 warning, and 6 notices
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ClangFormat.txt#L1
See https://docs.zephyrproject.org/latest/contribute/guidelines.html#clang-format for more details.
You may want to run clang-format on this change:
-#define DEV_CFG(_dev) ((const struct gpio_xlnx_ps_dev_cfg *)(_dev)->config)
+#define DEV_CFG(_dev) ((const struct gpio_xlnx_ps_dev_cfg *)(_dev)->config)
File:drivers/gpio/gpio_xlnx_ps.c
Line:24
You may want to run clang-format on this change:
- struct gpio_xlnx_ps_bank_dev_data *bank_data =
- dev_conf->bank_devices[bank]->data;
+ struct gpio_xlnx_ps_bank_dev_data *bank_data = dev_conf->bank_devices[bank]->data;
File:drivers/gpio/gpio_xlnx_ps.c
Line:60
You may want to run clang-format on this change:
-#define GPIO_XLNX_PS_DEV_DATA(idx)\
-static struct gpio_xlnx_ps_dev_data gpio_xlnx_ps##idx##_data = {\
- .base = 0x0,\
-};
+#define GPIO_XLNX_PS_DEV_DATA(idx) \
+ static struct gpio_xlnx_ps_dev_data gpio_xlnx_ps##idx##_data = { \
+ .base = 0x0, \
+ };
-#define GPIO_XLNX_PS_DEV_CONFIG(idx)\
-static const struct gpio_xlnx_ps_dev_cfg gpio_xlnx_ps##idx##_cfg = {\
- DEVICE_MMIO_NAMED_ROM_INIT(reg_base, DT_DRV_INST(idx)),\
- .bank_devices = gpio_xlnx_ps##idx##_banks,\
- .num_banks = ARRAY_SIZE(gpio_xlnx_ps##idx##_banks),\
- .config_func = gpio_xlnx_ps##idx##_irq_config\
-};
+#define GPIO_XLNX_PS_DEV_CONFIG(idx) \
+ static const struct gpio_xlnx_ps_dev_cfg gpio_xlnx_ps##idx##_cfg = { \
+ DEVICE_MMIO_NAMED_ROM_INIT(reg_base, DT_DRV_INST(idx)), \
+ .bank_devices = gpio_xlnx_ps##idx##_banks, \
+ .num_banks = ARRAY_SIZE(gpio_xlnx_ps##idx##_banks), \
+ .config_func = gpio_xlnx_ps##idx##_irq_config};
File:drivers/gpio/gpio_xlnx_ps.c
Line:134
You may want to run clang-format on this change:
-#define DEV_CFG(_dev) ((const struct gpio_xlnx_ps_bank_dev_cfg *)(_dev)->config)
+#define DEV_CFG(_dev) ((const struct gpio_xlnx_ps_bank_dev_cfg *)(_dev)->config)
File:drivers/gpio/gpio_xlnx_ps_bank.c
Line:25
You may want to run clang-format on this change:
-#define GPIO_XLNX_PS_BANK_INIT(idx)\
-static const struct gpio_xlnx_ps_bank_dev_cfg gpio_xlnx_ps_bank##idx##_cfg = {\
- .common = {\
- .port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(idx),\
- },\
- .bank_index = idx,\
-};\
-static struct gpio_xlnx_ps_bank_dev_data gpio_xlnx_ps_bank##idx##_data = {\
- .base = 0,\
-};\
-DEVICE_DT_INST_DEFINE(idx, gpio_xlnx_ps_bank_init, NULL,\
- &gpio_xlnx_ps_bank##idx##_data, &gpio_xlnx_ps_bank##idx##_cfg,\
- PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY, &gpio_xlnx_ps_bank_apis);
+#define GPIO_XLNX_PS_BANK_INIT(idx) \
+ static const struct gpio_xlnx_ps_bank_dev_cfg gpio_xlnx_ps_bank##idx##_cfg = { \
+ .common = \
+ { \
+ .port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(idx), \
+ }, \
+ .bank_index = idx, \
+ }; \
+ static struct gpio_xlnx_ps_bank_dev_data gpio_xlnx_ps_bank##idx##_data = { \
+ .base = 0, \
+ }; \
+ DEVICE_DT_INST_DEFINE(idx, gpio_xlnx_ps_bank_init, NULL, &gpio_xlnx_ps_bank##idx##_data, \
+ &gpio_xlnx_ps_bank##idx##_cfg, PRE_KERNEL_1, \
+ CONFIG_GPIO_INIT_PRIORITY, &gpio_xlnx_ps_bank_apis);
File:drivers/gpio/gpio_xlnx_ps_bank.c
Line:465
You may want to run clang-format
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Run Compliance Tests:
drivers/gpio/gpio_xlnx_ps.c#L24
drivers/gpio/gpio_xlnx_ps.c:24
-#define DEV_CFG(_dev) ((const struct gpio_xlnx_ps_dev_cfg *)(_dev)->config)
+#define DEV_CFG(_dev) ((const struct gpio_xlnx_ps_dev_cfg *)(_dev)->config)
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Run Compliance Tests:
drivers/gpio/gpio_xlnx_ps.c#L60
drivers/gpio/gpio_xlnx_ps.c:60
- struct gpio_xlnx_ps_bank_dev_data *bank_data =
- dev_conf->bank_devices[bank]->data;
+ struct gpio_xlnx_ps_bank_dev_data *bank_data = dev_conf->bank_devices[bank]->data;
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Run Compliance Tests:
drivers/gpio/gpio_xlnx_ps.c#L134
drivers/gpio/gpio_xlnx_ps.c:134
-#define GPIO_XLNX_PS_DEV_DATA(idx)\
-static struct gpio_xlnx_ps_dev_data gpio_xlnx_ps##idx##_data = {\
- .base = 0x0,\
-};
+#define GPIO_XLNX_PS_DEV_DATA(idx) \
+ static struct gpio_xlnx_ps_dev_data gpio_xlnx_ps##idx##_data = { \
+ .base = 0x0, \
+ };
-#define GPIO_XLNX_PS_DEV_CONFIG(idx)\
-static const struct gpio_xlnx_ps_dev_cfg gpio_xlnx_ps##idx##_cfg = {\
- DEVICE_MMIO_NAMED_ROM_INIT(reg_base, DT_DRV_INST(idx)),\
- .bank_devices = gpio_xlnx_ps##idx##_banks,\
- .num_banks = ARRAY_SIZE(gpio_xlnx_ps##idx##_banks),\
- .config_func = gpio_xlnx_ps##idx##_irq_config\
-};
+#define GPIO_XLNX_PS_DEV_CONFIG(idx) \
+ static const struct gpio_xlnx_ps_dev_cfg gpio_xlnx_ps##idx##_cfg = { \
+ DEVICE_MMIO_NAMED_ROM_INIT(reg_base, DT_DRV_INST(idx)), \
+ .bank_devices = gpio_xlnx_ps##idx##_banks, \
+ .num_banks = ARRAY_SIZE(gpio_xlnx_ps##idx##_banks), \
+ .config_func = gpio_xlnx_ps##idx##_irq_config};
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Run Compliance Tests:
drivers/gpio/gpio_xlnx_ps_bank.c#L25
drivers/gpio/gpio_xlnx_ps_bank.c:25
-#define DEV_CFG(_dev) ((const struct gpio_xlnx_ps_bank_dev_cfg *)(_dev)->config)
+#define DEV_CFG(_dev) ((const struct gpio_xlnx_ps_bank_dev_cfg *)(_dev)->config)
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Run Compliance Tests:
drivers/gpio/gpio_xlnx_ps_bank.c#L465
drivers/gpio/gpio_xlnx_ps_bank.c:465
-#define GPIO_XLNX_PS_BANK_INIT(idx)\
-static const struct gpio_xlnx_ps_bank_dev_cfg gpio_xlnx_ps_bank##idx##_cfg = {\
- .common = {\
- .port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(idx),\
- },\
- .bank_index = idx,\
-};\
-static struct gpio_xlnx_ps_bank_dev_data gpio_xlnx_ps_bank##idx##_data = {\
- .base = 0,\
-};\
-DEVICE_DT_INST_DEFINE(idx, gpio_xlnx_ps_bank_init, NULL,\
- &gpio_xlnx_ps_bank##idx##_data, &gpio_xlnx_ps_bank##idx##_cfg,\
- PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY, &gpio_xlnx_ps_bank_apis);
+#define GPIO_XLNX_PS_BANK_INIT(idx) \
+ static const struct gpio_xlnx_ps_bank_dev_cfg gpio_xlnx_ps_bank##idx##_cfg = { \
+ .common = \
+ { \
+ .port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(idx), \
+ }, \
+ .bank_index = idx, \
+ }; \
+ static struct gpio_xlnx_ps_bank_dev_data gpio_xlnx_ps_bank##idx##_data = { \
+ .base = 0, \
+ }; \
+ DEVICE_DT_INST_DEFINE(idx, gpio_xlnx_ps_bank_init, NULL, &gpio_xlnx_ps_bank##idx##_data, \
+ &gpio_xlnx_ps_bank##idx##_cfg, PRE_KERNEL_1, \
+ CONFIG_GPIO_INIT_PRIORITY, &gpio_xlnx_ps_bank_apis);
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Run Compliance Tests:
drivers/gpio/gpio_xlnx_ps_bank.h#L43
drivers/gpio/gpio_xlnx_ps_bank.h:43
-#define GPIO_XLNX_PS_BANK_MASK_DATA_LSW_REG (dev_data->base\
- + ((uint32_t)dev_conf->bank_index * 0x8))
-#define GPIO_XLNX_PS_BANK_MASK_DATA_MSW_REG ((dev_data->base + 0x04)\
- + ((uint32_t)dev_conf->bank_index * 0x8))
-#define GPIO_XLNX_PS_BANK_DATA_REG ((dev_data->base + 0x40)\
- + ((uint32_t)dev_conf->bank_index * 0x4))
-#define GPIO_XLNX_PS_BANK_DATA_RO_REG ((dev_data->base + 0x60)\
- + ((uint32_t)dev_conf->bank_index * 0x4))
-#define GPIO_XLNX_PS_BANK_DIRM_REG ((dev_data->base + 0x204)\
- + ((uint32_t)dev_conf->bank_index * 0x40))
-#define GPIO_XLNX_PS_BANK_OEN_REG ((dev_data->base + 0x208)\
- + ((uint32_t)dev_conf->bank_index * 0x40))
-#define GPIO_XLNX_PS_BANK_INT_MASK_REG ((dev_data->base + 0x20C)\
- + ((uint32_t)dev_conf->bank_index * 0x40))
-#define GPIO_XLNX_PS_BANK_INT_EN_REG ((dev_data->base + 0x210)\
- + ((uint32_t)dev_conf->bank_index * 0x40))
-#define GPIO_XLNX_PS_BANK_INT_DIS_REG ((dev_data->base + 0x214)\
- + ((uint32_t)dev_conf->bank_index * 0x40))
-#define GPIO_XLNX_PS_BANK_INT_STAT_REG ((dev_data->base + 0x218)\
- + ((uint32_t)dev_conf->bank_index * 0x40))
-#define GPIO_XLNX_PS_BANK_INT_TYPE_REG ((dev_data->base + 0x21C)\
- + ((uint32_t)dev_conf->bank_index * 0x40))
-#define GPIO_XLNX_PS_BANK_INT_POLARITY_REG ((dev_data->base + 0x220)\
- + ((uint32_t)dev_conf->bank_index * 0x40))
-#define GPIO_XLNX_PS_BANK_INT_ANY_REG ((dev_data->base + 0x224)\
- + ((uint32_t)dev_conf->bank_index * 0x40))
+#define GPIO_XLNX_PS_BANK_MASK_DATA_LSW_REG \
+ (dev_data->base + ((uint32_t)dev_conf->bank_index * 0x8))
+#define GPIO_XLNX_PS_BANK_MASK_DATA_MSW_REG \
+ ((dev_data->base + 0x04) + ((uint32_t)dev_conf->bank_index * 0x8))
+#define GPIO_XLNX_PS_BANK_DATA_REG \
+ ((dev_data->base + 0x40) + ((uint32_t)dev_conf->bank_index * 0x4))
+#define GPIO_XLNX_PS_BANK_DATA_RO_REG \
+ ((dev_data->base + 0x60) + ((uint32_t)dev_conf->bank_index * 0x4))
+#define GPIO_XLNX_PS_BANK_DIRM_REG \
+ ((dev_data->base + 0x204) + ((uint32_t)dev_conf->bank_index * 0x40))
+#define GPIO_XLNX_PS_BANK_OEN_REG \
+ ((dev_data->base + 0x208) + ((uint32_t)dev_conf->bank_index * 0x40))
+#define GPIO_XLNX_PS_BANK_INT_MASK_REG \
+ ((dev_data->base + 0x20C) + ((uint32_t)dev_conf->bank_index * 0x40))
+#define GPIO_XLNX_PS_BANK_INT_EN_REG \
+ ((dev_data->base + 0x210) + ((uint32_t)dev_conf->bank_index * 0x40))
+#define GPIO_XLNX_PS_BANK_INT_DIS_REG \
+ ((dev_data->base + 0x214) + ((uint32_t)dev_conf->bank_index * 0x40))
+#define GPIO_XLNX_PS_BANK_INT_STAT_REG \
+ ((dev_data->base + 0x218) + ((uint32_t)dev_conf->bank_index * 0x40))
+#define GPIO_XLNX_PS_BANK_INT_TYPE_REG \
+ ((dev_data->base + 0x21C) + ((uint32_t)dev_conf->bank_index * 0x40))
+#define GPIO_XLNX_PS_BANK_INT_POLARITY_REG \
+ ((dev_data->base + 0x220) + ((uint32_t)dev_conf->bank_index * 0x40))
+#define GPIO_XLNX_PS_BANK_INT_ANY_REG \
+ ((dev_data->base + 0x224) + ((uint32_t)dev_conf->bank_index * 0x40))
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