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driver: interrupt_controller: nuclei_eclic: fixed interrupt level and CLIC enable #75580

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merged 2 commits into from
Jul 12, 2024
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driver: interrupt_controller: nuclei_eclic: fixed interrupt level and CLIC enable #75580

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cbccc35
driver: interrupt_controller: nuclei_eclic: fixed interrupt level
jimmyzhe Jul 3, 2024
9124019
drivers: interrupt_controller: nuclei_eclic: do not modifiy trap entry
jimmyzhe Jul 8, 2024
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1 change: 0 additions & 1 deletion drivers/interrupt_controller/Kconfig.clic
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Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,6 @@ config NUCLEI_ECLIC
bool "Enhanced Core Local Interrupt Controller (ECLIC)"
default y
depends on DT_HAS_NUCLEI_ECLIC_ENABLED
select MULTI_LEVEL_INTERRUPTS
select RISCV_SOC_HAS_CUSTOM_IRQ_HANDLING if !RISCV_VECTORED_MODE
help
Interrupt controller for Nuclei SoC core.
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21 changes: 2 additions & 19 deletions drivers/interrupt_controller/intc_nuclei_eclic.c
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Expand Up @@ -12,7 +12,6 @@
#include <zephyr/arch/cpu.h>
#include <zephyr/sys/util.h>
#include <zephyr/device.h>
#include <zephyr/irq_multilevel.h>

#include <zephyr/sw_isr_table.h>
#include <zephyr/drivers/interrupt_controller/riscv_clic.h>
Expand Down Expand Up @@ -84,9 +83,6 @@ struct CLICCTRL {
volatile uint8_t INTCTRL;
};

/** ECLIC Mode mask for MTVT CSR Register */
#define ECLIC_MODE_MTVEC_Msk 3U

/** CLIC INTATTR: TRIG Mask */
#define CLIC_INTATTR_TRIG_Msk 0x3U

Expand All @@ -96,14 +92,6 @@ struct CLICCTRL {
#define ECLIC_CTRL ((volatile struct CLICCTRL *)(DT_REG_ADDR_BY_IDX(DT_NODELABEL(eclic), 3)))
#define ECLIC_CTRL_SIZE (DT_REG_SIZE_BY_IDX(DT_NODELABEL(eclic), 3))

#if CONFIG_3RD_LEVEL_INTERRUPTS
#define INTERRUPT_LEVEL 2
#elif CONFIG_2ND_LEVEL_INTERRUPTS
#define INTERRUPT_LEVEL 1
#else
#define INTERRUPT_LEVEL 0
#endif

static uint8_t nlbits;
static uint8_t intctlbits;
static uint8_t max_prio;
Expand Down Expand Up @@ -150,7 +138,7 @@ int riscv_clic_irq_is_enabled(uint32_t irq)
void riscv_clic_irq_priority_set(uint32_t irq, uint32_t pri, uint32_t flags)
{
const uint8_t prio = leftalign8(MIN(pri, max_prio), intctlbits);
const uint8_t level = leftalign8(MIN((irq_get_level(irq) - 1), max_level), nlbits);
const uint8_t level = leftalign8(max_level, nlbits);
const uint8_t intctrl = (prio | level) | (~intctrl_mask);

ECLIC_CTRL[irq].INTCTRL = intctrl;
Expand Down Expand Up @@ -180,18 +168,13 @@ void riscv_clic_irq_set_pending(uint32_t irq)

static int nuclei_eclic_init(const struct device *dev)
{
/* check hardware support required interrupt levels */
__ASSERT_NO_MSG(ECLIC_INFO.b.intctlbits >= INTERRUPT_LEVEL);

ECLIC_MTH.w = 0;
ECLIC_CFG.w = 0;
ECLIC_CFG.b.nlbits = INTERRUPT_LEVEL;
ECLIC_CFG.b.nlbits = 0;
for (int i = 0; i < ECLIC_CTRL_SIZE; i++) {
ECLIC_CTRL[i] = (struct CLICCTRL) { 0 };
}

csr_write(mtvec, ((csr_read(mtvec) & 0xFFFFFFC0) | ECLIC_MODE_MTVEC_Msk));

nlbits = ECLIC_CFG.b.nlbits;
intctlbits = ECLIC_INFO.b.intctlbits;
max_prio = mask8(intctlbits - nlbits);
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3 changes: 0 additions & 3 deletions soc/gd/gd32/gd32vf103/Kconfig.defconfig.gd32vf103
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Expand Up @@ -24,9 +24,6 @@ config NUM_IRQS
default 87 if NUCLEI_ECLIC
default 16 if !NUCLEI_ECLIC

config 2ND_LEVEL_INTERRUPTS
default y

config ARCH_IRQ_VECTOR_TABLE_ALIGN
default 512 if NUCLEI_ECLIC

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