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Add st_b_lcd40_dsi1_mb1166 display shield support for stm32f769i_disco board #74646

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Add st_b_lcd40_dsi1_mb1166 display shield support for stm32f769i_disco board #74646

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013b032
dts: arm: st: Add STM32F7 DSI host driver
ssekar15 Jun 21, 2024
a162834
dts: bindings: clock: Add pll-r for PLLDSICLK clock
ssekar15 Jun 21, 2024
df91691
boards: stm32f769i_disco: add pll-r for PLLDSICLK clock
ssekar15 Jun 21, 2024
436e99b
boards: shield: add dsi-lcd display header mapping for stm32h747i_disco
ssekar15 Jun 26, 2024
083f609
boards: shield: choose enhanced lvgl config as board dependent
ssekar15 Jun 28, 2024
e56c19d
boards: stm32f769i_disco: remove capacitive touch ft6202
ssekar15 Jun 21, 2024
687d174
boards: shield: add support for stm32f769i_disco board
ssekar15 Jun 21, 2024
1f9330b
samples: add disp_f769_disco to display samples with shield
ssekar15 Jul 4, 2024
d3e49e8
samples: add disp_f769_disco to display samples with shield
ssekar15 Jul 4, 2024
471d921
samples: add disp_f769_disco to display samples with shield
ssekar15 Jul 4, 2024
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18 changes: 2 additions & 16 deletions boards/shields/st_b_lcd40_dsi1_mb1166/Kconfig.defconfig
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Original file line number Diff line number Diff line change
Expand Up @@ -4,27 +4,13 @@

if SHIELD_ST_B_LCD40_DSI1_MB1166 || SHIELD_ST_B_LCD40_DSI1_MB1166_A09

# Double frame buffer maintained by lvgl.
if LVGL
orsource "boards/*.defconfig"
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Nit: this line should be outside of if LVGL


config STM32_LTDC_FB_NUM
default 0
if LVGL

config INPUT
default y

config LV_Z_VDB_SIZE
default 100

config LV_Z_DOUBLE_VDB
default y

config LV_Z_VBD_CUSTOM_SECTION
default y

config LV_Z_FULL_REFRESH
default y

config LV_Z_BITS_PER_PIXEL
default 32

Expand Down
5 changes: 5 additions & 0 deletions boards/shields/st_b_lcd40_dsi1_mb1166/boards/st_b_lcd40_dsi1_mb1166/stm32f769i_disco.conf
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Original file line number Diff line number Diff line change
@@ -0,0 +1,5 @@
# Copyright (c) 2024 Linumiz
# SPDX-License-Identifier: Apache-2.0

# Initialize after LTDC and MIPI-DSI
CONFIG_DISPLAY_OTM8009A_INIT_PRIORITY=87
22 changes: 22 additions & 0 deletions boards/shields/st_b_lcd40_dsi1_mb1166/boards/st_b_lcd40_dsi1_mb1166/stm32f769i_disco.overlay
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@@ -0,0 +1,22 @@
/*
* Copyright (c) 2024 Linumiz
*
* SPDX-License-Identifier: Apache-2.0
*/

&ltdc {
/* orisetech, otm8009a */
display-timings {
compatible = "zephyr,panel-timing";
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
hsync-len = <2>;
vsync-len = <1>;
hback-porch = <34>;
vback-porch = <15>;
hfront-porch = <34>;
vfront-porch = <16>;
};
};
6 changes: 6 additions & 0 deletions boards/shields/st_b_lcd40_dsi1_mb1166/boards/stm32f769i_disco.conf
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@@ -0,0 +1,6 @@
# Copyright (c) 2024 Linumiz
# SPDX-License-Identifier: Apache-2.0

CONFIG_MEMC=y
CONFIG_STM32_LTDC_RGB888=y
CONFIG_HEAP_MEM_POOL_SIZE=65536
41 changes: 41 additions & 0 deletions boards/shields/st_b_lcd40_dsi1_mb1166/boards/stm32f769i_disco.overlay
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/*
* Copyright (c) 2024 Linumiz
*
* SPDX-License-Identifier: Apache-2.0
*/

#include <zephyr/dt-bindings/display/panel.h>

/ {
lvgl_pointer {
compatible = "zephyr,lvgl-pointer-input";
input = <&ft5336>;
};

chosen {
zephyr,display = &ltdc;
};
};

&ltdc {
status = "okay";
ext-sdram = <&sdram1>;
width = <800>;
height = <480>;
def-back-color-red = <0>;
def-back-color-green = <0>;
def-back-color-blue = <0>;
pixel-format = <PANEL_PIXEL_FORMAT_RGB_888>;
};

&mipi_dsi {
status = "okay";

pll-ndiv = <100>;
pll-idf = <5>;
pll-odf = <0>;

vs-active-high;
hs-active-high;
de-active-high;
};
21 changes: 21 additions & 0 deletions boards/shields/st_b_lcd40_dsi1_mb1166/boards/stm32h747i_disco_stm32h747xx_m7.defconfig
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@@ -0,0 +1,21 @@
# Copyright (c) 2024 Linumiz
# SPDX-License-Identifier: Apache-2.0

if BOARD_STM32H747I_DISCO_STM32H747XX_M7
if LVGL

# Double frame buffer maintained by lvgl.
config STM32_LTDC_FB_NUM
default 0

config LV_Z_DOUBLE_VDB
default y

config LV_Z_VBD_CUSTOM_SECTION
default y

config LV_Z_FULL_REFRESH
default y

endif #LVGL
endif # BOARD_STM32H747I_DISCO_STM32H747XX_M7
12 changes: 0 additions & 12 deletions boards/shields/st_b_lcd40_dsi1_mb1166/boards/stm32h747i_disco_stm32h747xx_m7.overlay
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Expand Up @@ -61,15 +61,3 @@
hs-active-high;
de-active-high;
};

&i2c4 {
pinctrl-0 = <&i2c4_scl_pd12 &i2c4_sda_pd13>;
pinctrl-names = "default";
clock-frequency = <I2C_BITRATE_FAST>;
status = "okay";

ft5336: ft5336@38 {
compatible = "focaltech,ft5336";
reg = <0x38>;
};
};
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11 changes: 11 additions & 0 deletions boards/shields/st_b_lcd40_dsi1_mb1166/st_b_lcd40_dsi1_mb1166.overlay
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Expand Up @@ -4,6 +4,8 @@
* SPDX-License-Identifier: Apache-2.0
*/

#include <zephyr/dt-bindings/mipi_dsi/mipi_dsi.h>

&mipi_dsi {
otm8009a: otm8009a@0 {
status = "okay";
Expand All @@ -18,3 +20,12 @@
rotation = <90>;
};
};

&qsh_030_i2c {
ft5336: ft5336@38 {
compatible = "focaltech,ft5336";
reg = <0x38>;
int-gpios = <&dsi_lcd_qsh_030 4 0>;
status = "okay";
};
};
9 changes: 9 additions & 0 deletions boards/shields/st_b_lcd40_dsi1_mb1166/st_b_lcd40_dsi1_mb1166_a09.overlay
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Expand Up @@ -18,3 +18,12 @@
rotation = <90>;
};
};

&qsh_030_i2c {
ft5336: ft5336@38 {
compatible = "focaltech,ft5336";
reg = <0x38>;
int-gpios = <&dsi_lcd_qsh_030 4 0>;
status = "okay";
};
};
26 changes: 26 additions & 0 deletions boards/st/stm32f769i_disco/doc/index.rst
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Expand Up @@ -120,6 +120,9 @@ The Zephyr stm32f769i_disco board configuration supports the following hardware
+-----------+------------+-------------------------------------+
| TOUCH | off-chip | ft5336(FT6202) |
+-----------+------------+-------------------------------------+
| DISPLAY | off-chip | MIPI DSI Host with shield (MP1166) |
| | | st_b_lcd40_dsi1_mb1166 |
+-----------+------------+-------------------------------------+

Other hardware features are not yet supported on Zephyr porting.

Expand Down Expand Up @@ -162,6 +165,29 @@ The STM32F769I Discovery kit has up to 8 UARTs. The Zephyr console output is ass
which connected to the onboard ST-LINK/V2 Virtual COM port interface. Default communication
settings are 115200 8N1.

Display
=======

The STM32F769I Discovery kit has a dedicated DSI LCD connector **CN1**, where
the MB1166 (B-LCD40-DSI1) display extension board can be mounted. Enable display
support in Zephyr by adding the shield ``st_b_lcd40_dsi1_mb1166`` or
``st_b_lcd40_dsi1_mb1166_a09`` to your build command, for example:

.. zephyr-app-commands::
:zephyr-app: samples/drivers/display
:board: stm32f769i_disco
:shield: st_b_lcd40_dsi1_mb1166
:goals: build flash

.. note::
The shield comes in different hardware revisions, the MB1166-A09
is utilizing a NT35510 panel controller and shall specifically
use ``st_b_lcd40_dsi1_mb1166_a09`` as SHIELD when building.
Prior versions are utilizing an OTM8009a controller and shall
use shield name without postfix, that is: ``st_b_lcd40_dsi1_mb1166``.
Shield version is printed on a sticker placed below the two bottom
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mounting holes and has the format: MB1166-Axx.

Programming and Debugging
*************************

Expand Down
43 changes: 25 additions & 18 deletions boards/st/stm32f769i_disco/stm32f769i_disco.dts
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Expand Up @@ -66,11 +66,6 @@
};
};

lvgl_pointer {
compatible = "zephyr,lvgl-pointer-input";
input = <&ft6202>;
};

aliases {
led0 = &red_led_1;
led1 = &green_led_2;
Expand All @@ -85,6 +80,30 @@
zephyr,memory-region = "QSPI_AVAIL";
zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO) )>;
};

dsi_lcd_qsh_030: connector_dsi_lcd {
compatible = "st,dsi-lcd-qsh-030";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <4 0 &gpioi 13 0>, /* TOUCH_INT */
<35 0 &gpiod 12 0>, /* SCLK/MCLK */
<39 0 &gpiod 11 0>, /* I2S */
<40 0 &gpiob 9 0>, /* I2C4_SDA */
<44 0 &gpiob 8 0>, /* I2C4_SCL */
<45 0 &gpioa 8 0>, /* CEC_CLK */
<47 0 &gpioa 15 0>, /* CEC */
<49 0 &gpioj 2 0>, /* DSI_TE */
<53 0 &gpioi 14 0>, /* LCD_BL_CTRL */
<57 0 &gpioj 15 0>; /* DSI_RESET */
};
};

qsh_030_i2c: &i2c4 {
pinctrl-0 = <&i2c4_scl_pd12 &i2c4_sda_pb7>;
pinctrl-names = "default";
clock-frequency = <I2C_BITRATE_FAST>;
status = "okay";
};

&clk_hse {
Expand All @@ -97,6 +116,7 @@
mul-n = <432>;
div-p = <2>;
div-q = <9>;
div-r = <7>;
clocks = <&clk_hse>;
status = "okay";
};
Expand Down Expand Up @@ -134,19 +154,6 @@ arduino_serial: &usart6 {};
clock-frequency = <I2C_BITRATE_FAST>;
};

&i2c4 {
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pinctrl-0 = <&i2c4_scl_pd12 &i2c4_sda_pb7>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <I2C_BITRATE_FAST>;

ft6202: ft6202@2a {
compatible = "focaltech,ft5336";
reg = <0x2a>;
int-gpios = <&gpioi 13 0>;
};
};

&spi2 {
pinctrl-0 = <&spi2_nss_pa11 &spi2_sck_pa12 &spi2_miso_pb14 &spi2_mosi_pb15>;
pinctrl-names = "default";
Expand Down
24 changes: 24 additions & 0 deletions boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m7.dts
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Expand Up @@ -64,13 +64,37 @@
led1 = &orange_led_2;
sw0 = &wake_up;
};

dsi_lcd_qsh_030: connector_dsi_lcd {
compatible = "st,dsi-lcd-qsh-030";
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#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <4 0 &gpiok 7 0>, /* TOUCH_INT */
<35 0 &gpioe 5 0>, /* SCLK/MCLK */
<39 0 &gpioe 6 0>, /* I2S */
<40 0 &gpiod 13 0>, /* I2C4_SDA */
<44 0 &gpiod 12 0>, /* I2C4_SCL */
<45 0 &gpioa 8 0>, /* CEC_CLK */
<47 0 &gpiob 6 0>, /* CEC */
<49 0 &gpioj 2 0>, /* DSI_TE */
<53 0 &gpioj 12 0>, /* LCD_BL_CTRL */
<57 0 &gpiog 3 0>; /* DSI_RESET */
};
};

&clk_hse {
clock-frequency = <DT_FREQ_M(25)>;
status = "okay";
};

qsh_030_i2c: &i2c4 {
pinctrl-0 = <&i2c4_scl_pd12 &i2c4_sda_pd13>;
pinctrl-names = "default";
clock-frequency = <I2C_BITRATE_FAST>;
status = "okay";
};

&clk_hsi48 {
status = "okay";
};
Expand Down
12 changes: 12 additions & 0 deletions dts/arm/st/f7/stm32f765.dtsi
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Expand Up @@ -91,6 +91,18 @@
status = "disabled";
};

mipi_dsi: dsihost@40016C00 {
compatible = "st,stm32-mipi-dsi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40016C00 0x800>;
clock-names = "dsiclk", "refclk", "pixelclk";
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x08000000>,
<&rcc STM32_SRC_HSI NO_SEL>,
<&rcc STM32_SRC_PLL_R DSI_SEL(1)>;
resets = <&rctl STM32_RESET(APB2, 27U)>;
status = "disabled";
};
};

smbus4: smbus4 {
Expand Down
9 changes: 8 additions & 1 deletion dts/bindings/clock/st,stm32f7-pll-clock.yaml
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Expand Up @@ -6,11 +6,12 @@ description: |

Takes one of clk_hse or clk_hsi as input clock.

Up to 2 output clocks could be supported and for each output clock, the
Up to 3 output clocks could be supported and for each output clock, the
frequency can be computed with the following formula:

f(PLL_P) = f(VCO clock) / PLLP --> PLLCLK (System Clock)
f(PLL_Q) = f(VCO clock) / PLLQ --> PLL48CLK (Optional)
f(PLL_R) = f(VCO clock) / PLLR --> PLLDSICLK (Optional)

with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)

Expand Down Expand Up @@ -56,3 +57,9 @@ properties:
description: |
PLL division factor for PLL48CK
Valid range: 2 - 15

div-r:
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type: int
description: |
PLL division factor for PLLDSICLK
Valid range: 2 - 7
4 changes: 3 additions & 1 deletion samples/drivers/display/sample.yaml
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Expand Up @@ -132,7 +132,9 @@ tests:
fixture: fixture_display
sample.display.st_b_lcd40_dsi1_mb1166:
filter: dt_compat_enabled("orisetech,otm8009a")
platform_allow: stm32h747i_disco/stm32h747xx/m7
platform_allow:
- stm32h747i_disco/stm32h747xx/m7
- stm32f769i_disco
extra_args: SHIELD=st_b_lcd40_dsi1_mb1166
tags:
- display
Expand Down
4 changes: 3 additions & 1 deletion samples/modules/lvgl/demos/sample.yaml
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Expand Up @@ -26,7 +26,9 @@ tests:
- CONFIG_LV_Z_DEMO_WIDGETS=y
sample.modules.lvgl.demos.st_b_lcd40_dsi1_mb1166:
filter: dt_compat_enabled("orisetech,otm8009a")
platform_allow: stm32h747i_disco/stm32h747xx/m7
platform_allow:
- stm32h747i_disco/stm32h747xx/m7
- stm32f769i_disco
extra_args: SHIELD=st_b_lcd40_dsi1_mb1166
harness: console
harness_config:
Expand Down
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