ipc: icbmsg: Add support for POSIX arch targets #148033
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1 error, 1 warning, and 7 notices
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Run Compliance Tests
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check-warns:
ClangFormat.txt#L1
See https://docs.zephyrproject.org/latest/contribute/guidelines.html#clang-format for more details.
You may want to run clang-format on this change:
-#define DEFINE_BACKEND_BUFFER_DIR(i, dir) \
- NATIVE_SIMULATOR_IF \
+#define DEFINE_BACKEND_BUFFER_DIR(i, dir) \
+ NATIVE_SIMULATOR_IF \
char IPC##i##_##dir##_shm_buffer[DT_REG_SIZE(DT_INST_PHANDLE(i, dir##_region))];
-#define DEFINE_BACKEND_BUFFER(i) \
- DEFINE_BACKEND_BUFFER_DIR(i, tx) \
+#define DEFINE_BACKEND_BUFFER(i) \
+ DEFINE_BACKEND_BUFFER_DIR(i, tx) \
File:boards/native/nrf_bsim/ipc_backend.c
Line:44
You may want to run clang-format on this change:
-#define PBUF_CHECKS(name, mem_addr, size, dcache_align) \
-BUILD_ASSERT(dcache_align >= 0, \
- "Cache line size must be non negative."); \
-BUILD_ASSERT((size) > 0 && IS_PTR_ALIGNED_BYTES(size, _PBUF_IDX_SIZE), \
- "Incorrect size."); \
-BUILD_ASSERT(IS_PTR_ALIGNED_BYTES(mem_addr, MAX(dcache_align, _PBUF_IDX_SIZE)), \
- "Misaligned memory."); \
-BUILD_ASSERT(size >= (MAX(dcache_align, _PBUF_IDX_SIZE) + _PBUF_IDX_SIZE + \
- _PBUF_MIN_DATA_LEN), "Insufficient size.");
+#define PBUF_CHECKS(name, mem_addr, size, dcache_align) \
+ BUILD_ASSERT(dcache_align >= 0, "Cache line size must be non negative."); \
+ BUILD_ASSERT((size) > 0 && IS_PTR_ALIGNED_BYTES(size, _PBUF_IDX_SIZE), "Incorrect size."); \
+ BUILD_ASSERT(IS_PTR_ALIGNED_BYTES(mem_addr, MAX(dcache_align, _PBUF_IDX_SIZE)), \
+ "Misaligned memory."); \
+ BUILD_ASSERT( \
+ size >= (MAX(dcache_align, _PBUF_IDX_SIZE) + _PBUF_IDX_SIZE + _PBUF_MIN_DATA_LEN), \
+ "Insufficient size.");
File:include/zephyr/ipc/pbuf.h
Line:140
You may want to run clang-format on this change:
-#define PBUF_DEFINE(name, mem_addr, size, dcache_align) \
- PBUF_CHECKS(name, mem_addr, size, dcache_align) \
- static const struct pbuf_cfg cfg_##name = \
- PBUF_CFG_INIT(mem_addr, size, dcache_align); \
- static struct pbuf name = { \
- .cfg = &cfg_##name, \
+#define PBUF_DEFINE(name, mem_addr, size, dcache_align) \
+ PBUF_CHECKS(name, mem_addr, size, dcache_align) \
+ static const struct pbuf_cfg cfg_##name = PBUF_CFG_INIT(mem_addr, size, dcache_align); \
+ static struct pbuf name = { \
+ .cfg = &cfg_##name, \
File:include/zephyr/ipc/pbuf.h
Line:158
You may want to run clang-format on this change:
-
-
File:subsys/ipc/ipc_service/backends/ipc_icbmsg.c
Line:1218
You may want to run clang-format on this change:
-#define ICBMSG_BACKEND_PRE(i, direction) \
- extern char _IPC##i##_##direction##_shm_buffer[];
-#define GET_MEM_ADDR_INST(i, direction) \
- (const uintptr_t)_IPC##i##_##direction##_shm_buffer
+#define ICBMSG_BACKEND_PRE(i, direction) extern char _IPC##i##_##direction##_shm_buffer[];
+#define GET_MEM_ADDR_INST(i, direction) (const uintptr_t) _IPC##i##_##direction##_shm_buffer
File:subsys/ipc/ipc_service/backends/ipc_icbmsg.c
Line:1240
You may want to run clang-format on this change:
-#define GET_MEM_SIZE_INST(i, direction) \
+#define GET_MEM_SIZE_INST(i, direction) \
(GET_MEM_END_INST(i, direction) - GET_MEM_ADDR_INST(i, direction))
#else
-#define GET_MEM_SIZE_INST(i, direction) \
- DT_REG_SIZE(DT_INST_PHANDLE(i, direction##_region))
+#define GET_MEM_SIZE_INST(i, direction) DT_REG_SIZE(DT_INST_PHANDLE(i, direction##_region))
File:subsys/ipc/ipc_service/backends/ipc_icbmsg.c
Line:1
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Run Compliance Tests:
boards/native/nrf_bsim/ipc_backend.c#L44
boards/native/nrf_bsim/ipc_backend.c:44
-#define DEFINE_BACKEND_BUFFER_DIR(i, dir) \
- NATIVE_SIMULATOR_IF \
+#define DEFINE_BACKEND_BUFFER_DIR(i, dir) \
+ NATIVE_SIMULATOR_IF \
char IPC##i##_##dir##_shm_buffer[DT_REG_SIZE(DT_INST_PHANDLE(i, dir##_region))];
-#define DEFINE_BACKEND_BUFFER(i) \
- DEFINE_BACKEND_BUFFER_DIR(i, tx) \
+#define DEFINE_BACKEND_BUFFER(i) \
+ DEFINE_BACKEND_BUFFER_DIR(i, tx) \
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Run Compliance Tests:
include/zephyr/ipc/pbuf.h#L140
include/zephyr/ipc/pbuf.h:140
-#define PBUF_CHECKS(name, mem_addr, size, dcache_align) \
-BUILD_ASSERT(dcache_align >= 0, \
- "Cache line size must be non negative."); \
-BUILD_ASSERT((size) > 0 && IS_PTR_ALIGNED_BYTES(size, _PBUF_IDX_SIZE), \
- "Incorrect size."); \
-BUILD_ASSERT(IS_PTR_ALIGNED_BYTES(mem_addr, MAX(dcache_align, _PBUF_IDX_SIZE)), \
- "Misaligned memory."); \
-BUILD_ASSERT(size >= (MAX(dcache_align, _PBUF_IDX_SIZE) + _PBUF_IDX_SIZE + \
- _PBUF_MIN_DATA_LEN), "Insufficient size.");
+#define PBUF_CHECKS(name, mem_addr, size, dcache_align) \
+ BUILD_ASSERT(dcache_align >= 0, "Cache line size must be non negative."); \
+ BUILD_ASSERT((size) > 0 && IS_PTR_ALIGNED_BYTES(size, _PBUF_IDX_SIZE), "Incorrect size."); \
+ BUILD_ASSERT(IS_PTR_ALIGNED_BYTES(mem_addr, MAX(dcache_align, _PBUF_IDX_SIZE)), \
+ "Misaligned memory."); \
+ BUILD_ASSERT( \
+ size >= (MAX(dcache_align, _PBUF_IDX_SIZE) + _PBUF_IDX_SIZE + _PBUF_MIN_DATA_LEN), \
+ "Insufficient size.");
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Run Compliance Tests:
include/zephyr/ipc/pbuf.h#L158
include/zephyr/ipc/pbuf.h:158
-#define PBUF_DEFINE(name, mem_addr, size, dcache_align) \
- PBUF_CHECKS(name, mem_addr, size, dcache_align) \
- static const struct pbuf_cfg cfg_##name = \
- PBUF_CFG_INIT(mem_addr, size, dcache_align); \
- static struct pbuf name = { \
- .cfg = &cfg_##name, \
+#define PBUF_DEFINE(name, mem_addr, size, dcache_align) \
+ PBUF_CHECKS(name, mem_addr, size, dcache_align) \
+ static const struct pbuf_cfg cfg_##name = PBUF_CFG_INIT(mem_addr, size, dcache_align); \
+ static struct pbuf name = { \
+ .cfg = &cfg_##name, \
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Run Compliance Tests:
subsys/ipc/ipc_service/backends/ipc_icbmsg.c#L1218
subsys/ipc/ipc_service/backends/ipc_icbmsg.c:1218
-
-
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Run Compliance Tests:
subsys/ipc/ipc_service/backends/ipc_icbmsg.c#L1240
subsys/ipc/ipc_service/backends/ipc_icbmsg.c:1240
-#define ICBMSG_BACKEND_PRE(i, direction) \
- extern char _IPC##i##_##direction##_shm_buffer[];
-#define GET_MEM_ADDR_INST(i, direction) \
- (const uintptr_t)_IPC##i##_##direction##_shm_buffer
+#define ICBMSG_BACKEND_PRE(i, direction) extern char _IPC##i##_##direction##_shm_buffer[];
+#define GET_MEM_ADDR_INST(i, direction) (const uintptr_t) _IPC##i##_##direction##_shm_buffer
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Run Compliance Tests:
subsys/ipc/ipc_service/backends/ipc_icbmsg.c#L1259
subsys/ipc/ipc_service/backends/ipc_icbmsg.c:1259
-#define GET_MEM_SIZE_INST(i, direction) \
+#define GET_MEM_SIZE_INST(i, direction) \
(GET_MEM_END_INST(i, direction) - GET_MEM_ADDR_INST(i, direction))
#else
-#define GET_MEM_SIZE_INST(i, direction) \
- DT_REG_SIZE(DT_INST_PHANDLE(i, direction##_region))
+#define GET_MEM_SIZE_INST(i, direction) DT_REG_SIZE(DT_INST_PHANDLE(i, direction##_region))
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Run Compliance Tests:
subsys/ipc/ipc_service/backends/ipc_icbmsg.c#L1356
subsys/ipc/ipc_service/backends/ipc_icbmsg.c:1356
-#define DEFINE_BACKEND_DEVICE(i) \
- ICBMSG_BACKEND_PRE(i, tx); \
- ICBMSG_BACKEND_PRE(i, rx); \
- SYS_BITARRAY_DEFINE_STATIC(tx_usage_bitmap_##i, DT_INST_PROP(i, tx_blocks)); \
- SYS_BITARRAY_DEFINE_STATIC(rx_hold_bitmap_##i, DT_INST_PROP(i, rx_blocks)); \
- PBUF_DEFINE(tx_icbmsg_pb_##i, \
- GET_MEM_ADDR_INST(i, tx), \
- GET_ICMSG_SIZE_INST(i, tx, rx), \
- GET_CACHE_ALIGNMENT(i)); \
- PBUF_DEFINE(rx_icbmsg_pb_##i, \
- GET_MEM_ADDR_INST(i, rx), \
- GET_ICMSG_SIZE_INST(i, rx, tx), \
- GET_CACHE_ALIGNMENT(i)); \
- static struct backend_data backend_data_##i = { \
- .control_data = { \
- .tx_pb = &tx_icbmsg_pb_##i, \
- .rx_pb = &rx_icbmsg_pb_##i, \
- } \
- }; \
- static const struct icbmsg_config backend_config_##i = \
- { \
- .control_config = { \
- .mbox_tx = MBOX_DT_SPEC_INST_GET(i, tx), \
- .mbox_rx = MBOX_DT_SPEC_INST_GET(i, rx), \
- }, \
- .tx = { \
- .blocks_ptr = (uint8_t *)GET_BLOCKS_ADDR_INST(i, tx, rx), \
- .block_count = DT_INST_PROP(i, tx_blocks), \
- .block_size = GET_BLOCK_SIZE_INST(i, tx, rx), \
- }, \
- .rx = { \
- .blocks_ptr = (uint8_t *)GET_BLOCKS_ADDR_INST(i, rx, tx), \
- .block_count = DT_INST_PROP(i, rx_blocks), \
- .block_size = GET_BLOCK_SIZE_INST(i, rx, tx), \
- }, \
- .tx_usage_bitmap = &tx_usage_bitmap_##i, \
- .rx_hold_bitmap = &rx_hold_bitmap_##i, \
- }; \
- BUILD_ASSERT(IS_POWER_OF_TWO(GET_CACHE_ALIGNMENT(i)), \
- "This module supports only power of two cache alignment"); \
- BUILD_ASSERT((GET_BLOCK_SIZE_INST(i, tx, rx) > GET_CACHE_ALIGNMENT(i)) && \
- (GET_BLOCK_SIZE_INST(i, tx, rx) < \
- GET_MEM_SIZE_INST(i, tx)), \
- "TX region is too small for provided number of blocks"); \
- BUILD_ASSERT((GET_BLOCK_SIZE_INST(i, rx, tx) > GET_CACHE_ALIGNMENT(i)) && \
- (GET_BLOCK_SIZE_INST(i, rx, tx) < \
- GET_MEM_SIZE_INST(i, rx)), \
- "RX region is too small for provided number of blocks"); \
- BUILD_ASSERT(DT_INST_PROP(i, rx_blocks) <= 256, "Too many RX blocks"); \
- BUILD_ASSERT(DT_INST_PROP(i, tx_blocks) <= 256, "Too many TX blocks"); \
- DEVICE_DT_INST_DEFINE(i, \
- &backend_init, \
- NULL, \
- &backend_data_##i, \
- &backend_config_##i, \
- POST_KERNEL, \
- CONFIG_IPC_SERVICE_REG_BACKEND_PRIORITY, \
- &backend_ops);
+#define DEFINE_BACKEND_DEVICE(i) \
+ ICBMSG_BACKEND_PRE(i, tx); \
+ ICBMSG_BACKEND_PRE(i, rx); \
+ SYS_BITARRAY_DEFINE_STATIC(tx_usage_bitmap_##i, DT_INST_PROP(i, tx_blocks)); \
+ SYS_BITARRAY_DEFINE_STATIC(rx_hold_bitmap_##i, DT_INST_PROP(i, rx_blocks)); \
+ PBUF_DEFINE(tx_icbmsg_pb_##i, GET_MEM_ADDR_INST(i, tx), GET_ICMSG_SIZE_INST(i, tx, rx), \
+ GET_CACHE_ALIGNMENT(i)); \
+ PBUF_DEFINE(rx_icbmsg_pb_##i, GET_MEM_ADDR_INST(i, rx), GET_ICMSG_SIZE_INST(i, rx, tx), \
+ GET_CACHE_ALIGNMENT(i)); \
+ static struct backend_data backend_data_##i = {.control_data = { \
+ .tx_pb = &tx_icbmsg_pb_##i, \
+ .rx_pb = &rx_icbmsg_pb_##i, \
+ }}; \
+ static const struct icbmsg_config backend_config_##i = { \
+ .control_config = \
+ { \
+ .mbox_tx = MBOX_DT_SPEC_INST_GET(i, tx), \
+ .mbox_rx = MBOX_DT_SPEC_INST_GET(i, rx),
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