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[WIP] Tileable Routing Resource Graph Builder #2135

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[WIP] Tileable Routing Resource Graph Builder #2135

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Commits on Sep 19, 2022

  1. [vpr] debugging

    @tangxifan
    tangxifan committed Sep 19, 2022
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  2. [vtr] fixed a bug on sorting incoming edges for IPIN nodes: Only cons… 

    …ider a limited sides because channel nodes could be duplicated on multiple sides
    @tangxifan
    tangxifan committed Sep 19, 2022
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  3. [vpr] fixed a bug

    @tangxifan
    tangxifan committed Sep 19, 2022
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  4. [vtr] fixed a bug

    @tangxifan
    tangxifan committed Sep 19, 2022
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Commits on Sep 26, 2022

  1. [lib] replace the use of SIGSTKSZ which is not supported in Ubuntu 21… 

    ….04+
    @tangxifan
    tangxifan committed Sep 26, 2022
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Commits on Sep 28, 2022

  1. Merge branch 'master' into openfpga

    @tangxifan
    tangxifan authored Sep 28, 2022
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Commits on Sep 30, 2022

  1. [vpr] fixed a bug in finding direct connection in tileable rr_graph; … 

    …Remove verbose outputs
    @tangxifan
    tangxifan committed Sep 30, 2022
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  2. Merge branch 'openfpga' of https://github.com/verilog-to-routing/vtr-… 

    …verilog-to-routing into openfpga
    @tangxifan
    tangxifan committed Sep 30, 2022
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  3. [vpr] remove verbose outputs

    @tangxifan
    tangxifan committed Sep 30, 2022
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Commits on Oct 3, 2022

  1. [CMake] Added an option 'VTR_ENABLE_VERSION_UP_TO_DATE' which allows … 

    …users to skip version build (by default is always on). This can reduce build time when use VTR as a submodule
    @tangxifan
    tangxifan committed Oct 3, 2022
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  2. [cmake] bypass custom build on version number with an option

    @tangxifan
    tangxifan committed Oct 3, 2022
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  3. [cmake] rename option to be short 'VTR_ENABLE_VERSION'

    @tangxifan
    tangxifan committed Oct 3, 2022
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  4. Merge branch 'master' into openfpga

    @tangxifan
    tangxifan authored Oct 3, 2022
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Commits on Oct 4, 2022

  1. [vpr] enable tileable rr_graph when building routing structs

    @tangxifan
    tangxifan committed Oct 4, 2022
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  2. [vpr] code format

    @tangxifan
    tangxifan committed Oct 4, 2022
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  3. Merge branch 'openfpga' of https://github.com/verilog-to-routing/vtr-… 

    …verilog-to-routing into openfpga
    @tangxifan
    tangxifan committed Oct 4, 2022
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Commits on Oct 6, 2022

  1. Merge branch 'master' into openfpga

    @tangxifan
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Commits on Oct 31, 2022

  1. Merge branch 'master' into openfpga

    @tangxifan
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Commits on Nov 1, 2022

  1. [vpr] a more sophiscated version of read blif api

    @tangxifan
    tangxifan committed Nov 1, 2022
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  2. [test] update golden for new test

    @tangxifan
    tangxifan committed Nov 1, 2022
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  3. Merge branch 'master' into openfpga

    @tangxifan
    tangxifan authored Nov 1, 2022
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  4. [vpr] code format

    @tangxifan
    tangxifan committed Nov 1, 2022
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  5. Merge branch 'openfpga' of github.com:verilog-to-routing/vtr-verilog-… 

    …to-routing into openfpga
    @tangxifan
    tangxifan committed Nov 1, 2022
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Commits on Nov 17, 2022

  1. Merge branch 'master' into openfpga

    @tangxifan
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Commits on Nov 21, 2022

  1. Merge branch 'master' into openfpga

    @tangxifan
    tangxifan authored Nov 21, 2022
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Commits on Dec 7, 2022

  1. Merge branch 'master' into openfpga

    @tangxifan
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Commits on Jan 9, 2023

  1. Merge branch 'master' into openfpga

    @tangxifan
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Commits on Jan 18, 2023

  1. Merge branch 'master' into openfpga

    @tangxifan
    tangxifan authored Jan 18, 2023
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Commits on Jan 26, 2023

  1. Support route constraint.

    @Tulong4Dev
    Tulong4Dev committed Jan 26, 2023
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Commits on Jan 27, 2023

  1. Support route constraints.

    @Tulong4Dev
    Tulong4Dev committed Jan 27, 2023
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  2. Clean up code format.

    @Tulong4Dev
    Tulong4Dev committed Jan 27, 2023
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Commits on Feb 2, 2023

  1. Merge branch 'master' into openfpga

    @tangxifan
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Commits on Feb 3, 2023

  1. Make partition list and newly added route constraint optional in 

    constraint file.
    @Tulong4Dev
    Tulong4Dev committed Feb 3, 2023
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  2. Code format clang-7.

    @Tulong4Dev
    Tulong4Dev committed Feb 3, 2023
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Commits on Feb 15, 2023

  1. Route constraint for local clock and reset.

    @Tulong4Dev
    Tulong4Dev committed Feb 15, 2023
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Commits on Feb 16, 2023

  1. Merge pull request #2243 from verilog-to-routing/local_clock_reset 

    Route constraint for local clock and reset.
    @tangxifan
    tangxifan authored Feb 16, 2023
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Commits on Feb 26, 2023

  1. Update with regexpr and multi-files readin.

    @Tulong4Dev
    Tulong4Dev committed Feb 26, 2023
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  2. Merge branch 'master' into openfpga

    @tangxifan
    tangxifan authored Feb 26, 2023
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Commits on Mar 3, 2023

  1. Dev vpr constraint writer for route constrain.

    @Tulong4Dev
    Tulong4Dev committed Mar 3, 2023
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  2. Revert un-wanted changes made by editor.

    @Tulong4Dev
    Tulong4Dev committed Mar 3, 2023
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  3. Fix CLANG 6/7/10 compile issue.

    @Tulong4Dev
    Tulong4Dev committed Mar 3, 2023
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Commits on Mar 4, 2023

  1. [libs] add an invalidator to rrgraph builder so that we can modify th… 

    …e graph after build-up
    @tangxifan
    tangxifan committed Mar 4, 2023
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Commits on Mar 6, 2023

  1. [core] debugging

    @tangxifan
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Commits on Mar 7, 2023

  1. [core] debugging

    @tangxifan
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  2. Merge branch 'master' into route_constraint_dev

    @Tulong4Dev
    Tulong4Dev authored Mar 7, 2023
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  3. [core] debugging

    @tangxifan
    tangxifan committed Mar 7, 2023
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  4. [core] allow clock to be included optionally when building a gsb

    @tangxifan
    tangxifan committed Mar 7, 2023
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  5. [core] typo

    @tangxifan
    tangxifan committed Mar 7, 2023
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  6. [core] syntax

    @tangxifan
    tangxifan committed Mar 7, 2023
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  7. [core] debugging

    @tangxifan
    tangxifan committed Mar 7, 2023
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  8. [core] fixed a bug

    @tangxifan
    tangxifan committed Mar 7, 2023
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Commits on Mar 8, 2023

  1. Code clean up: fix memory leak issue.

    @Tulong4Dev
    Tulong4Dev committed Mar 8, 2023
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  2. Fix the memory leak.

    @Tulong4Dev
    Tulong4Dev committed Mar 8, 2023
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  3. Merge branch 'master' into route_constraint_dev

    @Tulong4Dev
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Commits on Mar 9, 2023

  1. Merge branch 'master' into route_constraint_dev

    @Tulong4Dev
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Commits on Mar 10, 2023

  1. add test.

    @Tulong4Dev
    Tulong4Dev committed Mar 10, 2023
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  2. Merge branch 'route_constraint_dev' of github.com:Tulong4Dev/vtr-veri… 

    …log-to-routing into route_constraint_dev
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    Tulong4Dev committed Mar 10, 2023
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Commits on Mar 11, 2023

  1. Update test.

    @Tulong4Dev
    Tulong4Dev committed Mar 11, 2023
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  2. fix write constraint; update with simple test.

    @Tulong4Dev
    Tulong4Dev committed Mar 11, 2023
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Commits on Mar 12, 2023

  1. Update new test golden result.

    @Tulong4Dev
    Tulong4Dev committed Mar 12, 2023
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  2. update document.

    @Tulong4Dev
    Tulong4Dev committed Mar 12, 2023
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Commits on Mar 14, 2023

  1. update golden results.

    @Tulong4Dev
    Tulong4Dev committed Mar 14, 2023
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  2. update golden result from release build.

    @Tulong4Dev
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Commits on Mar 17, 2023

  1. update golden.

    @Tulong4Dev
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Commits on Mar 18, 2023

  1. update golden result with deep-cleaned build.

    @Tulong4Dev
    Tulong4Dev committed Mar 18, 2023
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Commits on Mar 22, 2023

  1. clean up code based on review comments.

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    Tulong4Dev committed Mar 22, 2023
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Commits on Mar 24, 2023

  1. support route constraints.

    @Tulong4Dev
    Tulong4Dev committed Mar 24, 2023
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  2. Merge branch 'master' into openfpga

    @tangxifan
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Commits on Apr 15, 2023

  1. [core] resovle mering conflicts which causes compilation failures

    @tangxifan
    tangxifan committed Apr 15, 2023
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  2. Merge branch 'master' of github.com:verilog-to-routing/vtr-verilog-to… 

    …-routing into openfpga
    @tangxifan
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  3. [core] code format

    @tangxifan
    tangxifan committed Apr 15, 2023
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  4. [test] comment out testcase 'strong_vpr_constraints' due to a merging… 

    … conflict
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Commits on Apr 19, 2023

  1. add missing new line when writing place constraint

    @Tulong4Dev
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Commits on Apr 20, 2023

  1. Merge branch 'openfpga' into route_constraint_dev

    @Tulong4Dev
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  2. Merge pull request #2290 from Tulong4Dev/route_constraint_dev 

    Route constraint dev
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Commits on May 30, 2023

  1. Merge branch 'master' into openfpga

    @tangxifan
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Commits on Jun 6, 2023

  1. Merge branch 'master' into openfpga

    @tangxifan
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Commits on Jun 7, 2023

  1. [core] now adapt to latest api from DeviceGrid

    @tangxifan
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  2. Merge branch 'master' into openfpga

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Commits on Jun 8, 2023

  1. [core] fixed a bug due to mis-use of APIs

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Commits on Jul 25, 2023

  1. added call to .xmle and accept key from CMake macro

    @umariqbal-rs
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  2. Update install_dependencies.sh to install openssl

    @nadeemyaseen-rs
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Commits on Jul 31, 2023

  1. Code formatting

    @behzadmehmood-rs
    behzadmehmood-rs committed Jul 31, 2023
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  2. Update CMakeLists.txt to 3.5

    @nadeemyaseen-rs
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  3. Update CMakeLists.txt to bump the minimum version

    @nadeemyaseen-rs
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  4. Update CMakeLists.txt to bump the version

    @nadeemyaseen-rs
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  5. Update CMakeLists.txt to bump the CMake version

    @nadeemyaseen-rs
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Commits on Aug 1, 2023

  1. Merge pull request #1 from RapidSilicon/encrypt_decrypt 

    Adding Encryption and Decryption Tool for XML
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  2. Update hostsetup.sh to install openssl

    @nadeemyaseen-rs
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Commits on Aug 7, 2023

  1. Merge branch 'master' into openfpga

    @tangxifan
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Commits on Aug 8, 2023

  1. [lib] syntax due to the layer support

    @tangxifan
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  2. [core] remove dead data type (not sure why git merge does not apply a… 

    …utomatically)
    @tangxifan
    tangxifan committed Aug 8, 2023
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  3. resolving conflicts

    @umariqbal-rs
    umariqbal-rs committed Aug 8, 2023
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  4. Merge branch 'openfpga' into openfpga

    @umariqbal-rs
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  5. [core] adapting tileable rr_graph to layers

    @tangxifan
    tangxifan committed Aug 8, 2023
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  6. Update hostsetup.sh to install dev package of openssl

    @nadeemyaseen-rs
    nadeemyaseen-rs authored Aug 8, 2023
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  7. resolving conflicts

    @umariqbal-rs
    umariqbal-rs committed Aug 8, 2023
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  8. Merge branch 'openfpga' into openfpga

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  9. [core] fixed broken API call due to layer upgrades

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Commits on Aug 10, 2023

  1. Merge branch 'openfpga' into openfpga

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  2. Update install_apt_packages.sh to install openssl package

    @nadeemyaseen-rs
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  3. [core] add support on shrink boundary on device grid when building ti… 

    …leable routing resource graph
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  1. [core] debugging

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  2. [core] code format

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  3. [core] now shrink boundary is working

    @tangxifan
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  4. Merge branch 'openfpga' into openfpga

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  5. [core] code format and clean up warnings

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  6. [core] remove debugging messages

    @tangxifan
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  7. [lib] code format

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  1. Merge branch 'openfpga' into openfpga

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Commits on Aug 18, 2023

  1. [lib] fixed a bug when supporting subtile index in custom pin location

    @tangxifan
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Commits on Aug 22, 2023

  1. [core] tileable rr graph builder supports different segments in x and… 

    … Y axis
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  2. [core] syntax

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Commits on Aug 24, 2023

  1. Merge branch 'verilog-to-routing:openfpga' into openfpga

    @umariqbal-rs
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  2. updating CMAKE in libencrypt to take libpugixml as linking library

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  1. [core] add corner case to judge the existence of switch block in gsb

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  2. [core] fixed a bug

    @tangxifan
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  3. [core] format

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  4. [core] fixed a bug

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Commits on Aug 27, 2023

  1. Merge pull request #2358 from RapidSilicon/openfpga 

    Adding Encryption and Decryption Tool for XML
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  1. Merge branch 'master' into openfpga

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  2. [core] fixed a bug in build where tbb is not used.

    @tangxifan
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Commits on Oct 11, 2023

  1. Add 'not found' check for finding file extension of arch xml

    @coolbreeze413
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  1. Fix clang-14 formatting complaints

    @coolbreeze413
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  2. Fix missing separator in .github/scripts/hostsetup.sh

    @coolbreeze413
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  3. Merge pull request #2418 from coolbreeze413/openfpga 

    Add 'not found' check for finding file extension of arch xml
    @tangxifan
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  4. Merge branch 'master' into openfpga

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Commits on Nov 3, 2023

  1. [core] remove tbb lines

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  2. [core] syntax

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Commits on Nov 13, 2023

  1. Merge branch 'master' into openfpga

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  2. [vpr] support a new option opin2all_sides` for tileable routing arc… 

    …hitecture
    @tangxifan
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  3. [core] code format

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  4. [core] add a new option concat_pass_wire to tileable rr graph gen… 

    …erator
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  5. [core] code format

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  6. Merge branch 'master' of github.com:verilog-to-routing/vtr-verilog-to… 

    …-routing into openfpga
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  7. [core] resolve conflicts

    @tangxifan
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  8. [core] fixed a bug

    @tangxifan
    tangxifan committed Nov 13, 2023
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  9. [core] fixing the bug

    @tangxifan
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  10. [core] syntax

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  11. [core] syntax

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  12. [core] syntaxc

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  13. [core] fixed a bug

    @tangxifan
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  14. [core] fixed a bug

    @tangxifan
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  15. [core] fixed a bug

    @tangxifan
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  16. [core] debug

    @tangxifan
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Commits on Apr 12, 2024

  1. Merge branch 'master' into openfpga

    @tangxifan
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  2. [vpr] add missing support on tileable routing

    @tangxifan
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  1. Merge branch 'master' into openfpga

    @tangxifan
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  1. [vpr] now use the switch index from direct defintion

    @tangxifan
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  2. [test] remove out-of-date koios entry

    @tangxifan
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  3. [vpr] syntax and sanity checks

    @tangxifan
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  4. [lib] support multiple ptc number for rr graph I/O

    @tangxifan
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  5. [lib] update rr graph I/O auto-gen files

    @tangxifan
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  6. [lib] update rr graph reader

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  7. [lib] fixed a few bugs

    @tangxifan
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  8. [vpr] fixed a bug where rr graph I/O always require node_ptc_nums

    @tangxifan
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Commits on May 4, 2024

  1. [vpr] debugging

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  2. [lib] debugging

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  3. [lib] fixed the bug in I/O of rrgraph. Seems that the ostream require… 

    … std:string after to_string conversion
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  4. [lib] add resize for ptc nums

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  5. [lib] fixed the bug on rr graph io. Should use temp_string_

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Commits on May 5, 2024

  1. [lib] fixed a bug on node lookup assignment in RR graph I/O when supp… 

    …orting multiple ptc
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  2. [lib] now add rc data for CHANX and CHANY nodes in tileable rr graph

    @tangxifan
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  3. [test] now use L1 and L4 in the tileable arch

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  4. [test] add new testcases for tileable rr graph

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Commits on May 7, 2024

  1. [core] fixed a bug where Y-axis segments may not be found

    @tangxifan
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Commits on May 19, 2024

  1. [core] add methods to identify opins for connection blocks

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  2. [core] syntax

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Commits on May 20, 2024

  1. Merge branch 'master' into openfpga

    @tangxifan
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  2. [core] fixed a bug on rr gsb when sorting edges from OPINs

    @tangxifan
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Commits on May 21, 2024

  1. [core] add more debuggin messages

    @tangxifan
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Commits on Jun 4, 2024

  1. [vpr] bypass 0-fan-in node in power estimator

    @tangxifan
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  2. Merge branch 'master' into openfpga

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  1. Merge branch 'master' into openfpga

    @tangxifan
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Commits on Jun 6, 2024

  1. resolve merge conflicts.

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  2. Merge pull request #2591 from verilog-to-routing/resolve_merge_conflict 

    resolve merge conflicts.
    @tangxifan
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  3. Merge branch 'master' into openfpga

    @tangxifan
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Commits on Jun 9, 2024

  1. Merge branch 'master' into openfpga

    @tangxifan
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  1. Merge branch 'master' into openfpga

    @tangxifan
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  2. Merge branch 'master' into openfpga

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Commits on Jun 19, 2024

  1. Merge branch 'master' into openfpga

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Commits on Jun 24, 2024

  1. Merge branch 'master' into openfpga

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Commits on Jun 25, 2024

  1. Removing warnings from libencrypt and libdecrypt

    @behzadmehmood
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Commits on Jul 3, 2024

  1. Merge branch 'master' of github.com:verilog-to-routing/vtr-verilog-to… 

    …-routing into openfpga
    @tangxifan
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  2. [vpr] add a new option to enable perimeter cbx and cby

    @tangxifan
    tangxifan committed Jul 3, 2024
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  3. [vpr] updating tileable rr graph generator

    @tangxifan
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  4. [vpr] upgraded tileable rr_graph to support perimeter cb

    @tangxifan
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  5. [vpr] syntax

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  6. [test] add perimeter_cb to strong test

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  7. [test] add new test

    @tangxifan
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  8. [vpr] fixed a bug on access invalid grid nodes

    @tangxifan
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  9. [lib] relax check_rr_node on (x, y) range as now CHANX and CHANY can … 

    …occur at perimeter
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  10. Merge branch 'master' into openfpga

    @tangxifan
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Commits on Jul 4, 2024

  1. [vpr] typo on debug string

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  2. [vpr] fix minor bug where sort edge is not applicable to boundary gsb… 

    …s when perimeter_cb is on
    @tangxifan
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  3. [vpr] fixing a bug where sorted edges are not located

    @tangxifan
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  4. [vpr] now when cb on perimeter, I/O pins can access three sides

    @tangxifan
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  5. [vpr] syntax

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  6. [vpr] syntax

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  7. [vpr] syntax

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    tangxifan committed Jul 4, 2024
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  8. [vpr] fixed a bug where perimeter cb are not connected to adjancet sbs

    @tangxifan
    tangxifan committed Jul 4, 2024
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  9. [vpr] fixing some bugs in rr gsb

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    tangxifan committed Jul 4, 2024
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  10. [core] debug

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    tangxifan committed Jul 4, 2024
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Commits on Jul 5, 2024

  1. [vpr] now change to a simpler rr gsb coordinate system: grid is moved… 

    … to the bottom-left corner
    @tangxifan
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  2. [vpr] update gsb builder in tileable rr graph for changing the coordi… 

    …ndate system of gsb
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    tangxifan committed Jul 5, 2024
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  3. [vpr] syntax

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    tangxifan committed Jul 5, 2024
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  4. [vpr] debugging

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    tangxifan committed Jul 5, 2024
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  5. [core] fixed a bug where gsb nodes are not correctly added

    @tangxifan
    tangxifan committed Jul 5, 2024
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  6. [core] debug

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    tangxifan committed Jul 5, 2024
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  7. [core] debugging

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    tangxifan committed Jul 5, 2024
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  8. [core] debug

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    tangxifan committed Jul 5, 2024
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  9. [core] debug

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    tangxifan committed Jul 5, 2024
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  10. [core] fixed a critical bug

    @tangxifan
    tangxifan committed Jul 5, 2024
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Commits on Jul 8, 2024

  1. Updating libencryption/libdecryption for compatibility with openssl3

    @behzadmehmood
    behzadmehmood committed Jul 8, 2024
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  2. Not dumping decrypted xml

    @behzadmehmood
    behzadmehmood committed Jul 8, 2024
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  3. Commenting unused variables in pugixml_loc.cpp

    @behzadmehmood
    behzadmehmood committed Jul 8, 2024
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  4. Merge branch 'openfpga' of https://github.com/verilog-to-routing/vtr-… 

    …verilog-to-routing into rem_warnings
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    behzadmehmood committed Jul 8, 2024
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  5. [core] fixed a bug where sb may go out of boundary

    @tangxifan
    tangxifan committed Jul 8, 2024
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  6. [core] code format

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    tangxifan committed Jul 8, 2024
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  7. [core] debugging

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    tangxifan committed Jul 8, 2024
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Commits on Jul 9, 2024

  1. Minor changes for code clean-up

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    behzadmehmood committed Jul 9, 2024
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  2. Updating code to avoid possible memory leaks

    @behzadmehmood
    behzadmehmood committed Jul 9, 2024
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  3. Dynamically allocating memory for session key

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    behzadmehmood committed Jul 9, 2024
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Commits on Jul 10, 2024

  1. Adding test for XML encryption/decryption

    @behzadmehmood
    behzadmehmood committed Jul 10, 2024
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  2. Updating CMake for libencrypt

    @behzadmehmood
    behzadmehmood committed Jul 10, 2024
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  3. Correcting typo and removing valgrind call from workflow file

    @behzadmehmood
    behzadmehmood committed Jul 10, 2024
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  4. Updating build path for Test_Encryption_Decryption

    @behzadmehmood
    behzadmehmood committed Jul 10, 2024
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Commits on Jul 13, 2024

  1. added unit test for libdecryption

    @NadeemYaseen
    NadeemYaseen committed Jul 13, 2024
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Commits on Jul 15, 2024

  1. Merge remote-tracking branch 'origin/openfpga' into rem_warnings

    @behzadmehmood
    behzadmehmood committed Jul 15, 2024
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Commits on Jul 30, 2024

  1. Merge pull request #2629 from verilog-to-routing/rem_warnings 

    Removing warnings from libencrypt and libdecrypt
    @tangxifan
    tangxifan authored Jul 30, 2024
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  2. Merge branch 'master' into openfpga

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    tangxifan authored Jul 30, 2024
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Commits on Jul 31, 2024

  1. Merge branch 'master' into openfpga

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    tangxifan authored Jul 31, 2024
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Commits on Aug 8, 2024

  1. Merge branch 'master' into openfpga

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    tangxifan authored Aug 8, 2024
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Commits on Aug 28, 2024

  1. Merge branch 'master' into openfpga

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    tangxifan authored Aug 28, 2024
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Commits on Oct 7, 2024

  1. Merge branch 'master' into openfpga

    @tangxifan
    tangxifan authored Oct 7, 2024
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  2. [core] adapt to side var changes

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    tangxifan committed Oct 7, 2024
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  3. [core] fixed a bug where sink node cannot be mirror

    @tangxifan
    tangxifan committed Oct 7, 2024
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  4. Merge branch 'master' into openfpga

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    tangxifan authored Oct 7, 2024
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Commits on Oct 8, 2024

  1. Merge branch 'master' into openfpga

    @tangxifan
    tangxifan authored Oct 8, 2024
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  2. Merge branch 'master' into openfpga

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    tangxifan authored Oct 8, 2024
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Commits on Oct 10, 2024

  1. Merge branch 'master' into openfpga

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    tangxifan authored Oct 10, 2024
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Commits on Oct 17, 2024

  1. Merge branch 'master' into openfpga

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    tangxifan authored Oct 17, 2024
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  2. [core] fix the bug where skip sync-routing results are not applicable… 

    … to flat routing
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    tangxifan committed Oct 17, 2024
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Commits on Oct 23, 2024

  1. Merge branch 'master' into openfpga

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    tangxifan authored Oct 23, 2024
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Commits on Oct 28, 2024

  1. Merge branch 'master' into openfpga

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    tangxifan authored Oct 28, 2024
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Commits on Nov 4, 2024

  1. Merge branch 'master' into openfpga

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    tangxifan authored Nov 4, 2024
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Commits on Nov 12, 2024

  1. Merge branch 'master' into openfpga

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    tangxifan authored Nov 12, 2024
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Commits on Nov 13, 2024

  1. [lib] syntax

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    tangxifan committed Nov 13, 2024
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  2. [core] resolve conflicts

    @tangxifan
    tangxifan committed Nov 13, 2024
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  3. [lib] clang syntax

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    tangxifan committed Nov 13, 2024
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