[WIP] Tileable Routing Resource Graph Builder

[tangxifan]

Description

Bring the tileable routing resource graph builder from OpenFPGA to VPR.
Full details about the tileable routing resource graph builder can be found at

X. Tang, E. Giacomin, A. Alacchi and P. Gaillardon, "A Study on Switch Block Patterns for Tileable FPGA Routing Architectures," 2019 International Conference on Field-Programmable Technology (ICFPT), 2019, pp. 247-250, doi: 10.1109/ICFPT47387.2019.00039.

fpt2019_final.pdf

https://ieeexplore.ieee.org/document/8977869

Related Issue

Motivation and Context

The tileable routing resource graph builder is an alternative routing resource graph builder than the existing one in VTR.
Being compatible with existing data structures (RRGraphView and RRGraphBuilder), this new feature enables VTR to support FPGA devices created by OpenFPGA.

User Interface
The tileable routing resource graph builder can be enabled through XML syntax in architecture description langauge

<layout tileable="true">
    <auto_layout aspect_ratio="1.000000">
      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
      <perimeter type="io" priority="100"/>
      <corners type="EMPTY" priority="101"/>
      <!--Fill with 'clb'-->
      <fill type="clb" priority="10"/>
    </auto_layout>
</layout>
<!-- Switch block with a mix of Subset and Universal patterns -->
<device>
  <switch_block type="subset" fs="3" sub_type="universal" sub_fs="3"/>
</device>

The tileable rr_graph generator also supports mixed switch block pattern: The wires which start and end in a switch block have a switch bock pattern, while the wires which pass through a switch block can have another switch block pattern.

• Added a new option '--skip_sync_clustering_and_routing_results', soi that users can force to bypass the synchronization on clustering results based on routing optimization results. This is made for OpenFPGA's repacker, which has a built-in synchronization that supports more flexible net swapping during routing optimization.
• Replace the use of SIGSTKSZ in libcatch2 which is not supported in Ubuntu 21.04+
• Added CMake option VTR_ENABLE_VERSION (by default is on), which allows developers to skip version build when integrating VTR as a submodule
• Reworked API is_real_param() in read_blif.cpp (borrowed from another feature branch of Antmicro)

Known Limitations

• No support on dedicated clock network
• No support on custom switch block patterns

Checklist

• Add code changes
• Update documentation - Clarity limitations on XML syntax
• Add regression tests

Bugs/Issues found

• num_class in type_descriptor is not used. It is always set to 0 regardless the list size of class_inf. Suggest to remove it.
• See bugs in resize_node(). It may mistakenly reset node_lookup() when calling it incrementally. When calling reserve_node to pre-allocate memory, such bugs can be bypassed.
• libcapn'proto relies on an absolute path when compiling dependency. This will cause build errors when using VTR as a submodule
• When option --write_block_usage is enabled, the block usage is only shown in std:cout or an external file. As a result, the information is not included in the vpr_stdout.log since it is not using VTR_LOG

vtr-verilog-to-routing/vpr/src/base/ShowSetup.cpp

Lines 174 to 179 in 50b56f3

	void writeClusteredNetlistStats(std::string block_usage_filename) {
	const auto stats = ClusteredNetlistStats();
	// Print out the human readable version to stdout
	stats.write(ClusteredNetlistStats::OutputFormat::HumanReadable, std::cout);

How Has This Been Tested?

Here are a list of regression tests to added, in order to support existing features/options in customizing routing resource graphs.

• Basic tileable rr graph - a homogeneous FPGA sizing from a small array to a medium/large array
• Strong tileable - a heterogeneous FPGA sizing from a small array to a medium/large array
• Strong wire types: Use multiple wire types and different connectivity patterns in architecture description
• Strong chan_width_tileable: Support different (x, y) routing channel widths
• Strong SB pattern: support mixed switch block pattern, e.g., Wilton + Universal

Types of changes

• Bug fix (change which fixes an issue)
• New feature (change which adds functionality)
• Breaking change (fix or feature that would cause existing functionality to change)

Checklist:

• My change requires a change to the documentation
• I have updated the documentation accordingly
• I have added tests to cover my changes
• All new and existing tests passed