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Move emitRef from Verilog to backend #487

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Move emitRef from Verilog to backend #487

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Commits on Aug 10, 2015

  1. Move emitDef from Verilog to backend; 

    Removed seemily redundant nameAll as called further down;
Not passing tests as emitRef is called twice in some situations;
Valid code is generated but does not start at T0
    Stephen Tridgell committed Aug 10, 2015
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Commits on Aug 11, 2015

  1. Put the first nameAll back in

    Stephen Tridgell committed Aug 11, 2015
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Commits on Jan 20, 2016

  1. Merge branch 'master' into nameDeclarations 

    Conflicts:
	src/main/scala/Backend.scala
    Stephen Tridgell committed Jan 20, 2016
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Commits on Mar 6, 2016

  1. Merge branch 'master' into nameDeclarations 

    Conflicts:
	src/main/scala/Backend.scala
    Stephen Tridgell committed Mar 6, 2016
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  2. Update MultiClockSuite_Comp_1.v success code. 

    Don't use T0 for both clock and wire.
    @ucbjrl
    ucbjrl authored and Stephen Tridgell committed Mar 6, 2016
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