⚠️ Rework SoC bus system and memory map (#648)

CHANGELOG.md

@@ -33,6 +33,9 @@ mimpid = 0x01080200 => Version 01.08.02.00 => v1.8.2
 
 | Date (*dd.mm.yyyy*) | Version | Comment |
 |:-------------------:|:-------:|:--------|
+| 16.07.2023 | 1.8.6.5 | :warning: **rework SoC bus system & memory map - part 3**: re-enforce PMAs (physical memory attributes); [#648](https://github.com/stnolting/neorv32/pull/648) |
+| 15.07.2023 | 1.8.6.4 | :warning: **rework SoC bus system & memory map - part 2**: move IO address decoding to central IO switch; add i-cache uncached accesses; [#648](https://github.com/stnolting/neorv32/pull/648) |
+| 14.07.2023 | 1.8.6.3 | :warning: **rework SoC bus system & memory map - part 1**: add central bus gateway to control core accesses to the main address regions; [#648](https://github.com/stnolting/neorv32/pull/648) |
 | 14.07.2023 | 1.8.6.2 | minor rtl edits; [#646](https://github.com/stnolting/neorv32/pull/646) |
 | 30.06.2023 | 1.8.6.1 | minor rtl edits, cleanups and optimizations; [#641](https://github.com/stnolting/neorv32/pull/641) |
 | 27.06.2023 | [**:rocket:1.8.6**](https://github.com/stnolting/neorv32/releases/tag/v1.8.6) | **New release** |

README.md

@@ -129,11 +129,10 @@ see the [_open-source architecture ID list_](https://github.com/riscv/riscv-isa-
 *Unprivileged ISA Specification* ([pdf](https://github.com/stnolting/neorv32/blob/main/docs/references/riscv-spec.pdf))
 and *Privileged Architecture Specification* ([pdf](https://github.com/stnolting/neorv32/blob/main/docs/references/riscv-privileged.pdf)).
 * `machine` and `user` privilege modes
-* implements **all** standard RISC-V exceptions and interrupts (including MTI, MEI & MSI)
-* 16 fast interrupt request channels as NEORV32-specific extension
+* implements **all** standard RISC-V exceptions and interrupts + 16 fast interrupt request channels as NEORV32-specific extension
 * custom functions unit ([CFU](https://stnolting.github.io/neorv32/#_custom_functions_unit_cfu) as `Zxcfu` ISA extension)
 for _custom RISC-V instructions_ (R3-type, R4-type and R5-type);
-* _intrinsic_ libraries for the `Zicond`, `Zfinx` and `Zxcfu` ISA extensions
+* _intrinsic_ libraries for CPU extensions that are not yet supported by GCC
 
 **Memories**
 
@@ -176,13 +175,13 @@ allows booting application code via UART or from external SPI flash
 
 * **true** random number generator ([TRNG](https://stnolting.github.io/neorv32/#_true_random_number_generator_trng)) based
 on the [neoTRNG](https://github.com/stnolting/neoTRNG)
-* execute-in-place module ([XIP](https://stnolting.github.io/neorv32/#_execute_in_place_module_xip)) to execute code directly from SPI flash
+* execute-in-place module ([XIP](https://stnolting.github.io/neorv32/#_execute_in_place_module_xip)) to execute code right from a SPI flash
 * custom functions subsystem ([CFS](https://stnolting.github.io/neorv32/#_custom_functions_subsystem_cfs))
 for custom tightly-coupled co-processors, accelerators or interfaces
 * direct memory access controller ([DMA](https://stnolting.github.io/neorv32/#_direct_memory_access_controller_dma)) for CPU-independent
 data transfers and conversions
 * cyclic redundancy check unit ([DMA](https://stnolting.github.io/neorv32/#_cyclic_redundancy_check_crc)) to test
-data integrity (CRC8/CRC16/CRC32)
+data integrity (CRC8/16/32)
 
 **Debugging**
 
@@ -278,7 +277,7 @@ This overview provides some *quick links* to the most important sections of the
 * **[NEORV32 Project](https://stnolting.github.io/neorv32/#_overview) - introduction**
   * [Rationale](https://stnolting.github.io/neorv32/#_rationale) - why? how come? what for?
   * [Key Features](https://stnolting.github.io/neorv32/#_project_key_features) - what makes it special
-  * [Structure](https://stnolting.github.io/neorv32/#_project_folder_structure) - folders and RTL files
+  * [Structure](https://stnolting.github.io/neorv32/#_project_folder_structure) - folders, RTL files and compile order
   * [Metrics](https://stnolting.github.io/neorv32/#_fpga_implementation_results) - FPGA implementation and performance evaluation
 
 ### :electric_plug: Hardware Overview

docs/datasheet/cpu.adoc

@@ -69,7 +69,7 @@ overlapping operation of fetch and execute) at a reduced hardware footprint (due
 As a Von-Neumann machine, the CPU provides independent interfaces for instruction fetch and data access. However,
 these two bus interfaces are merged into a single processor-internal bus via a prioritizing bus switch (data accesses
 have higher priority). Hence, _all_ memory addresses including peripheral devices are mapped to a single unified 32-bit
-address space (see section <<_cpu_data_and_instruction_access>>).
+<<_address_space>>.
 
 [NOTE]
 The CPU does not perform any speculative/out-of-order operations at all. Hence, it is not vulnerable to security issues
@@ -821,9 +821,9 @@ The processor-internal modules do not have to respond within a fixed cycle amoun
 However, the bus transaction has to be completed (= acknowledged) within a certain **response time window**. This time window
 is defined by the global `max_proc_int_response_time_c` constant (default = 15 cycles; the processor's VHDL package file
 `rtl/neorv32_package.vhd`). It defines the maximum number of cycles after which a non-responding bus request (i.e. no `ack`
-and no `*err` signal) will **time out** and will raise a bus access fault exception. The <<_internal_bus_monitor_buskeeper>>
+and no `*err` signal) will **time out** and will raise a bus access fault exception. The memory GATEWAY
 keeps track of all bus transactions to enforce this time window. If any bus operations times out - for example when
-accessing "address space holes" - the BUSKEEPER will issue a bus error to the CPU that will raise the according bus
+accessing "address space holes" - the GATEWAY will issue a bus error to the CPU that will raise the according bus
 exception.
 
 .Access Boundaries

docs/datasheet/on_chip_debugger.adoc

@@ -414,14 +414,14 @@ the _program buffer_, the _data buffer_ and the _status register_. The program b
 status register do not fully occupy the 64-byte-wide sections and are mirrored to fill the entire section.
 
 .DM CPU access - address map (divided into four sections)
-[cols="^2,^4,^2,<7"]
+[cols="^2,^2,<5"]
 [options="header",grid="rows"]
 |=======================
-| Base address | Name [VHDL package]              | Actual size | Description
-| `0xfffff800` | `dm_code_base_c` (= `dm_base_c`) |    64 bytes | ROM for the "park loop" code
-| `0xfffff840` | `dm_pbuf_base_c`                 |    16 bytes | Program buffer, provided by DM
-| `0xfffff880` | `dm_data_base_c`                 |     4 bytes | Data buffer (`dm.data0`)
-| `0xfffff8c0` | `dm_sreg_base_c`                 |     4 bytes | Control and status register
+| Base address | Actual size | Description
+| `0xffffff00` |    64 bytes | ROM for the "park loop" code
+| `0xffffff40` |    16 bytes | Program buffer, provided by DM
+| `0xffffff80` |     4 bytes | Data buffer (`dm.data0`)
+| `0xffffffc0` |     4 bytes | Control and status register
 |=======================
 
 .DM Register Access