cleanups

stnolting · Jul 17, 2023 · c606d2b · c606d2b
1 parent 9b1c4e6
commit c606d2b
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Showing 3 changed files with 6 additions and 6 deletions.
diff --git a/docs/datasheet/software.adoc b/docs/datasheet/software.adoc
@@ -318,7 +318,7 @@ while `LENGTH` defines its size in bytes. The attributes are configured indirect
 __neorv32_rom_size = DEFINED(__neorv32_rom_size) ? __neorv32_rom_size : 2048M;
 __neorv32_ram_size = DEFINED(__neorv32_ram_size) ? __neorv32_ram_size : 8K;
 
-/* Default section base addresses - do not change this unless the hardware-defined address space layout is changed! */
+/* Default section base addresses */
 __neorv32_rom_base = DEFINED(__neorv32_rom_base) ? __neorv32_rom_base : 0x00000000; /* = VHDL package's "ispace_base_c" */
 __neorv32_ram_base = DEFINED(__neorv32_ram_base) ? __neorv32_ram_base : 0x80000000; /* = VHDL package's "dspace_base_c" */
 ----
@@ -373,8 +373,8 @@ section and to clear the `.bss` section (faster!).
 :sectnums:
 ==== RAM Layout
 
-The default NEORV32 linker script uses all of the defined RAM (linker script memory section `ram`) to create four areas.
-Note that depending on the application some areas might not be existent at all.
+The default NEORV32 linker script uses all of the defined RAM (linker script memory section `ram`) to several sections.
+Note that depending on the application some sections might have zero size.
 
 .Default RAM Layout
 image::ram_layout.png[400]

diff --git a/rtl/core/neorv32_intercon.vhd b/rtl/core/neorv32_intercon.vhd
@@ -404,8 +404,8 @@ begin
     boot_req_o.re <= main_req_i.re and port_en(port_boot_c);
     --
     io_req        <= main_req_i;
-    io_req.we     <= main_req_i.we and port_en(port_io_c);-- and and_reduce_f(main_req_i.ben) ; -- PMA: 32-bit writes only
-    io_req.re     <= main_req_i.re and port_en(port_io_c);-- and (not main_req_i.src); -- PMA: no-execute
+    io_req.we     <= main_req_i.we and port_en(port_io_c);
+    io_req.re     <= main_req_i.re and port_en(port_io_c);
     --
     ext_req_o     <= main_req_i;
     ext_req_o.we  <= main_req_i.we and port_en(port_ext_c);

diff --git a/sw/common/neorv32.ld b/sw/common/neorv32.ld
@@ -63,7 +63,7 @@ __neorv32_ram_size = DEFINED(__neorv32_ram_size) ? __neorv32_ram_size : 8K;
 /* Default HEAP size (= 0; no heap at all) */
 __neorv32_heap_size = DEFINED(__neorv32_heap_size) ? __neorv32_heap_size : 0;
 
-/* Default section base addresses - do not change this unless the hardware-defined address space layout is changed! */
+/* Default section base addresses */
 __neorv32_rom_base = DEFINED(__neorv32_rom_base) ? __neorv32_rom_base : 0x00000000; /* = VHDL package's "ispace_base_c" */
 __neorv32_ram_base = DEFINED(__neorv32_ram_base) ? __neorv32_ram_base : 0x80000000; /* = VHDL package's "dspace_base_c" */