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feat(smhc): add smhc peripheral pins and fix some issues. #14

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merged 1 commit into from
Oct 9, 2024
Merged

feat(smhc): add smhc peripheral pins and fix some issues. #14

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11 changes: 4 additions & 7 deletions src/ccu.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -813,17 +813,14 @@ impl ClockGate for DRAM {
#[inline]
unsafe fn reset(ccu: &ccu::RegisterBlock) {
let dram_bgr = ccu.dram_bgr.read();
ccu.dram_bgr
.write(dram_bgr.gate_mask().assert_reset());
ccu.dram_bgr.write(dram_bgr.gate_mask().assert_reset());
let dram_bgr = ccu.dram_bgr.read();
ccu.dram_bgr
.write(dram_bgr.gate_pass().deassert_reset());
ccu.dram_bgr.write(dram_bgr.gate_pass().deassert_reset());
}
#[inline]
unsafe fn free(ccu: &ccu::RegisterBlock) {
let dram_bgr = ccu.dram_bgr.read();
ccu.dram_bgr
.write(dram_bgr.gate_mask().assert_reset());
ccu.dram_bgr.write(dram_bgr.gate_mask().assert_reset());
}
}

Expand All @@ -842,7 +839,7 @@ impl ClockConfig for DRAM {
dram_clk
.set_clock_source(source)
.set_factor_m(factor_m)
.set_factor_n(factor_n)
.set_factor_n(factor_n),
)
}
}
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2 changes: 1 addition & 1 deletion src/gpio.rs
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Expand Up @@ -359,7 +359,7 @@ impl<'a, const P: char, const N: u8> Disabled<'a, P, N> {
set_mode(self)
}

// Internal constructor for ROM runtime. Do not use.
/// Internal constructor for ROM runtime. Do not use.
#[doc(hidden)]
#[inline(always)]
pub const unsafe fn __new(gpio: &'a RegisterBlock) -> Self {
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8 changes: 4 additions & 4 deletions src/smhc.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -63,18 +63,18 @@ pub struct GlobalControl(u32);
/// FIFO access mode.
#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)]
pub enum AccessMode {
// Dma bus.
/// Dma bus.
Dma,
// Ahb bus.
/// Ahb bus.
Ahb,
}

/// DDR mode.
#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)]
pub enum DdrMode {
// SDR mode.
/// SDR mode.
Sdr,
// DDR mode.
/// DDR mode.
Ddr,
}

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13 changes: 12 additions & 1 deletion src/wafer/d1.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -174,7 +174,18 @@ impl_pins_trait! {
('F', 3, 2): smhc::Cmd;
('F', 4, 2): smhc::Data<3>;
('F', 5, 2): smhc::Data<2>;
// TODO other SDC{0,1,2} pins. Please refer to Section 9.7.3.2 'GPIO Multiplex Function'.
('G', 0, 2): smhc::Clk;
('G', 1, 2): smhc::Cmd;
('G', 2, 2): smhc::Data<0>;
('G', 3, 2): smhc::Data<1>;
('G', 4, 2): smhc::Data<2>;
('G', 5, 2): smhc::Data<3>;
('C', 2, 3): smhc::Clk;
('C', 3, 3): smhc::Cmd;
('C', 4, 3): smhc::Data<2>;
('C', 5, 3): smhc::Data<1>;
('C', 6, 3): smhc::Data<0>;
('C', 7, 3): smhc::Data<3>;
}

/// Allwinner D1 interrupts.
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