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issue #401 - First round of changes to improve clarity of document. Removed mention of U-mode interrupts. #403
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…emoved mention of U-mode interrupts.
| smclicshv | Selective Hardware Vectoring for M-mode | ||
| smclicconfig | Allows implementations to support different parameterizations of CLIC extensions | ||
| | ||
|=== |
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this table is giving an error in the build process
is specified using the Indirect CSR Access extension method (Smcsrind/Sscsrind). A CSR accessible via | ||
indirect CSR access may or may not be accessible via another method such as memory-mapped access. | ||
Access to CLIC registers clicintctl[i], clicintattr[i], clicintip[i], clicintie[i], and clicinttrig[i] | ||
utilizes the Indirect CSR Access extension (Smcsrind/Sscsrind). Implementations may support |
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good i like it.
0x1000+i | 23:16 | RW clicintctl[i x 4 + 2] | 23:16 | RW clicintattr[i x 4 + 2] | setting for interrupt i x 4 + 2 | | ||
0x1000+i | 31:24 | RW clicintctl[i x 4 + 3] | 31:24 | RW clicintattr[i x 4 + 3] | setting for interrupt i x 4 + 3 | | ||
---- | ||
All CLIC registers are visible to M-mode. |
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shouldn't this be covered by the privileged spec?
In this miselect offset range, | ||
Each mireg register controls the clic level/priority setting of four interrupts | ||
Each mireg2 register controls the clic attribute setting of four interrupts | ||
NOTE: Since accessing `clicintip[__i__]`, `clicintie[__i__]`, `clicintattr[__i__]`, |
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not sure this note is needed.
1 01 Supervisor S | ||
2 10 Reserved | ||
3 11 Machine M | ||
Mode Value Name Abbreviation |
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why actually repeat this here at all?
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when not in CLIC mode, {cause} has the CLINT mode format. | ||
When not in CLIC mode, {cause} has the CLINT mode format. |
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should be xcause?
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No, the ASCIIDOC converts {cause} to xcause automatically. BTW, this happens everywhere and for other CSR names too.
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got it. I commented it because above there was a fix for xIE or so. So maybe it should be done there too.
i went roughly half through this PR for now. I gave some comments, but I don't think I can review this as a whole. |
I’ll look at the table build error. Works fine in my VSCode preview but I should be building this first before doing a PR. Sorry, I’m still ramping up on these sorts of tasks.
From: Christian Herber ***@***.***>
Sent: Wednesday, September 4, 2024 1:01 AM
To: riscv/riscv-fast-interrupt ***@***.***>
Cc: James Ball ***@***.***>; Author ***@***.***>
Subject: Re: [riscv/riscv-fast-interrupt] issue #401 - First round of changes to improve clarity of document. Removed mention of U-mode interrupts. (PR #403)
WARNING: This email originated from outside of Qualcomm. Please be wary of any links or attachments, and do not enable macros.
@christian-herber-nxp commented on this pull request.
________________________________
In src/clic.adoc<#403 (comment)>:
+interrupt input. The mideleg CSR (if present) no longer controls interrupt delegation.
+
+=== CLIC Extensions Summary
+
+This table provides a summary of the extensions supported by the CLIC.
+
+[%autowidth]
+|===
+| Extension Name | Description
+
+| smclic | CLIC support for M-mode
+| ssclic | CLIC support for S-mode
+| smclicshv | Selective Hardware Vectoring for M-mode
+| smclicconfig | Allows implementations to support different parameterizations of CLIC extensions
+|
+|===
this table is giving an error in the build process
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|
I did the merge since it was approved (hope I'm supposed to do this, I'm still learning GitHub) |
looks good. I would recommend to do a squash merge in future, to make to have one commit on the main branch per PR. |
This PR contains my many updates to the CLIC spec to improve clarity. Based on discussions in the Fast Interrupt TG, I removed references to user-mode interrupts to simplify the specification. If the N extension someday moves forward towards ratification, we can add in support to the CLIC specification at that time.