Lsu allow spec load exec #92

h0lyalg0rithm · 2023-10-04T16:03:26Z

This PR introduces the following

Allows loads to perform Virtual address to Physical address translation before older loads complete.
This can be configured using a parameter in the LSU
Allow non blocking cache lookup requests. Depends on Non Blocking Cache Implementation #91 for the cache to support this feature
Implements Ready queue - Simulator only structure to speed up instruction lookup in the LSU.
Mitigates data hazards introduced by instructions running out of order
The length of the different stages of the LSU pipeline can be configured through the parameters.

arupc

Can we add some documentation on what are the purpose of various in and out ports of LSU, at least between LSU & MMU and LSU & Dache

LSU / MMU interface has 3 input ports and 1 output:

output:
- out_mmu_lookup_req
inputs:
- in_mmu_lookup_req
- in_mmu_lookup_ack
- in_mmu_free_req

Similary, LSU / Dache interface has 3 input ports and 1 output port:

output:
- out_cache_lookup_req
inputs:
- in_cache_lookup_req
- in_cache_lookup_ack
- in_cache_free_req

core/LSU.cpp

core/LSU.hpp

core/LSU.cpp

core/LSU.hpp

arupc

Can you please explain what these priorities / states mean and when they would occur? Not sure I understand what is meant by 'mss ack' and 'another oustanding miss finish'

                HIGHEST = 0,
                __FIRST = HIGHEST,
                CACHE_RELOAD,   // Receive mss ack, waiting for cache re-access
                CACHE_PENDING,  // Wait for another outstanding miss finish
                MMU_RELOAD,     // Receive for mss ack, waiting for mmu re-access
                MMU_PENDING,    // Wait for another outstanding miss finish
                NEW_DISP,       // Wait for new issue
                LOWEST,

Does NEW_DISP simply mean dispatched and waiting to be issued?

arupc

One drawback of having a enumeration of IssuePriority is that it somewhat ties us to having one issue priority policy. If we want to allow multiple issue priority policies as a paramter, it may be difficult to with IssuePriority enumerator.

For that, we should keep the CACHE/MMU_RELOAD/PENDING info as states of the LoadStoreInfo class and allow different policies to decide which one to issue.

This can be done in a different PR after this is merged in.

ghost

This is a great start. A few items here and there to tackle, obviously

core/LSU.hpp

core/MemoryAccessInfo.hpp

test/sim/lsu_arch_configs/small_core.yaml

core/LSU.cpp

h0lyalg0rithm · 2023-10-17T14:36:20Z

Can you please explain what these priorities / states mean and when they would occur? Not sure I understand what is meant by 'mss ack' and 'another oustanding miss finish'
                HIGHEST = 0,
                __FIRST = HIGHEST,
                CACHE_RELOAD,   // Receive mss ack, waiting for cache re-access
                CACHE_PENDING,  // Wait for another outstanding miss finish
                MMU_RELOAD,     // Receive for mss ack, waiting for mmu re-access
                MMU_PENDING,    // Wait for another outstanding miss finish
                NEW_DISP,       // Wait for new issue
                LOWEST,
Does NEW_DISP simply mean dispatched and waiting to be issued?

The priority values are used to select the instruction that needs to be issued.
NEW_DISP is the priority of an instruction which has its operands ready(depends on the spec_load_exec) and is ready to be issued.
CACHE_RELOAD on the other hand is the priority placed on an instruction which had previously had a cache miss and now the cache is ready so it wake up the instruction by setting its priority to CACHE_RELOAD. As the priority is higher it is selected to be issued.

arupc · 2023-10-18T02:14:21Z

Can you please explain what these priorities / states mean and when they would occur? Not sure I understand what is meant by 'mss ack' and 'another oustanding miss finish'
                HIGHEST = 0,
                __FIRST = HIGHEST,
                CACHE_RELOAD,   // Receive mss ack, waiting for cache re-access
                CACHE_PENDING,  // Wait for another outstanding miss finish
                MMU_RELOAD,     // Receive for mss ack, waiting for mmu re-access
                MMU_PENDING,    // Wait for another outstanding miss finish
                NEW_DISP,       // Wait for new issue
                LOWEST,
Does NEW_DISP simply mean dispatched and waiting to be issued?
The priority values are used to select the instruction that needs to be issued. NEW_DISP is the priority of an instruction which has its operands ready(depends on the spec_load_exec) and is ready to be issued. CACHE_RELOAD on the other hand is the priority placed on an instruction which had previously had a cache miss and now the cache is ready so it wake up the instruction by setting its priority to CACHE_RELOAD. As the priority is higher it is selected to be issued.

arupc · 2023-10-18T03:57:25Z

Can you please explain what these priorities / states mean and when they would occur? Not sure I understand what is meant by 'mss ack' and 'another oustanding miss finish'
                HIGHEST = 0,
                __FIRST = HIGHEST,
                CACHE_RELOAD,   // Receive mss ack, waiting for cache re-access
                CACHE_PENDING,  // Wait for another outstanding miss finish
                MMU_RELOAD,     // Receive for mss ack, waiting for mmu re-access
                MMU_PENDING,    // Wait for another outstanding miss finish
                NEW_DISP,       // Wait for new issue
                LOWEST,
Does NEW_DISP simply mean dispatched and waiting to be issued?
The priority values are used to select the instruction that needs to be issued. NEW_DISP is the priority of an instruction which has its operands ready(depends on the spec_load_exec) and is ready to be issued. CACHE_RELOAD on the other hand is the priority placed on an instruction which had previously had a cache miss and now the cache is ready so it wake up the instruction by setting its priority to CACHE_RELOAD. As the priority is higher it is selected to be issued.

How would we implement an issue policy which prioritizes requests with MMU pending over request with CACHE pending?

How about instead of IssuePriority enum, we keep something equivalent to bitmasks, specifying for each instance of LoadStoreInstInfo, whether MMU_LOOKUP is needed and has been satisfied, CACHE_LOOKUP is needed and has been satisfied.

This would enable implementation of various issue policies, without changing the enum. But this can be done as apart of another MR

core/LSU.cpp

ghost · 2023-12-11T21:52:18Z

Did you test this with Kunal L2Cache stuff? Does it work?

h0lyalg0rithm · 2023-12-13T15:32:56Z

Did you test this with Kunal L2Cache stuff? Does it work?

I havent been able to test it out, I tried to keep the PR in sync with master

h0lyalg0rithm · 2023-12-14T19:56:34Z

@klingaard I rebuilt the project(cleant cache, cmake build folder) I ran both coremark and drhystone and both of them ran successfully.
I have the logs from valgrind but there were tons of errors but not sure if they are false positive

ERROR SUMMARY: 10000034 errors from 41 contexts

…src/riscv-perf-model into lsu_allow_spec_load_exec

…_exec

klingaard · 2023-12-14T22:08:23Z

I'll take a look this evening.

core/LSU.cpp

…_exec' into lsu_allow_spec_load_exec

ghost · 2023-12-15T16:17:24Z

I forgot one more thing. 😄 Can you run run clang format on the LSU since you're the last person to make major changes to it?

…_exec

klingaard · 2023-12-15T16:34:05Z

@h0lyalg0rithm, I hijacked your PR to update the names of the CI regressions (and merged with master). FYI...

h0lyalg0rithm · 2023-12-16T20:58:19Z

@klingaard I ran the formatter on most of the files I touched.I left some like Inst.hpp and sim/Olympia.cpp.
I found an duplicate config in the clang format file. Could you please check I removed the correct one

.clang-format

klingaard · 2023-12-18T14:47:05Z

Thanks for running the formatter. One last, last thing, promise! Can you update the Description field on what this PR did -- the changes it implemented and new expected behaviors. That will be the final commit message.

h0lyalg0rithm · 2023-12-18T22:25:08Z

I updated the PR description

This PR introduces the following - Allows loads to perform Virtual address to Physical address translation before older loads complete This can be configured using a parameter in the LSU (`allow_speculative_load_exec`) - Allow non blocking cache lookup requests. Depends on riscv-software-src#91 for the cache to support this feature - Implements Ready queue - simulator-only structure to speed up instruction lookup in the LSU - Mitigates data hazards introduced by instructions running out of order - The length of the different stages of the LSU pipeline can be configured through the parameters. --------- Co-authored-by: Knute Lingaard <[email protected]>

klingaard · 2024-01-25T21:48:56Z

core/LSU.hpp

+            PARAMETER(uint32_t, replay_issue_delay, 3, "Replay Issue delay")
+            // LSU microarchitecture parameters
+            PARAMETER(
+                bool, allow_speculative_load_exec, true,


@h0lyalg0rithm is this parameter's boolean meaning inverted? I'm looking at the code and if this is set to true, then the LS will NOT allow a load to bypass an older store.

@klingaard This parameter by default is set to true, so it should allow a load to complete before a store

h0lyalg0rithm force-pushed the lsu_allow_spec_load_exec branch 4 times, most recently from 7f2402b to 7e40e55 Compare October 12, 2023 01:32

h0lyalg0rithm marked this pull request as ready for review October 12, 2023 08:02

h0lyalg0rithm force-pushed the lsu_allow_spec_load_exec branch from 7e40e55 to 11626be Compare October 12, 2023 08:06

arupc reviewed Oct 13, 2023

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h0lyalg0rithm force-pushed the lsu_allow_spec_load_exec branch from 2f4c527 to 9e23b97 Compare October 18, 2023 12:00

h0lyalg0rithm added 5 commits October 18, 2023 14:14

Feature: allow_spec_load_exec

7b78330

Dont use replay buffer for non speculative loads

f699284

Fix update logic

65855f5

LSU pipeline with variable stage length

be1f7b6

Tests for LSU

759d5d1

Uncomment tests

c643dd6

klingaard assigned h0lyalg0rithm Dec 13, 2023

klingaard self-requested a review December 13, 2023 16:12

klingaard added 2 commits December 14, 2023 16:06

Merge branch 'lsu_allow_spec_load_exec' of github.com:riscv-software-…

43c31b6

…src/riscv-perf-model into lsu_allow_spec_load_exec

Merge remote-tracking branch 'origin/master' into lsu_allow_spec_load…

152d7d4

…_exec

klingaard reviewed Dec 14, 2023

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h0lyalg0rithm and others added 5 commits December 15, 2023 13:41

Fix mem issue based on CR

5fe4da5

Merge remote-tracking branch 'refs/remotes/origin/lsu_allow_spec_load…

8389520

…_exec' into lsu_allow_spec_load_exec

Merged with master; fixed another valgrind issue

bd54600

Use newly created pointer

9803509

Remove const

985822e

klingaard added 2 commits December 15, 2023 10:23

Merge remote-tracking branch 'origin/master' into lsu_allow_spec_load…

76d0fd9

…_exec

Changed the names of the regression targets

0b89502

h0lyalg0rithm added 2 commits December 16, 2023 21:56

Run Clang format on code

95b3c00

Remove duplicate formatting option

4429179

h0lyalg0rithm commented Dec 16, 2023

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klingaard merged commit f4088b8 into master Dec 19, 2023
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danbone mentioned this pull request Jan 8, 2024

Improve Load/Store Unit #57

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Lsu allow spec load exec #92

Lsu allow spec load exec #92

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Lsu allow spec load exec #92

Lsu allow spec load exec #92

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