Skip to content

Commit

Permalink
Lsu allow spec load exec (riscv-software-src#92)
Browse files Browse the repository at this point in the history
This PR introduces the following
- Allows loads to perform Virtual address to Physical address
translation before older loads complete
  This can be configured using a parameter in the LSU (`allow_speculative_load_exec`)
- Allow non blocking cache lookup requests. Depends on riscv-software-src#91 for the cache
to support this feature
- Implements Ready queue - simulator-only structure to speed up
instruction lookup in the LSU
- Mitigates data hazards introduced by instructions running out of order
- The length of the different stages of the LSU pipeline can be
configured through the parameters.

---------

Co-authored-by: Knute Lingaard <[email protected]>
  • Loading branch information
h0lyalg0rithm and klingaard authored Dec 19, 2023
1 parent 38d41e4 commit 30b7961
Show file tree
Hide file tree
Showing 23 changed files with 1,831 additions and 828 deletions.
1 change: 0 additions & 1 deletion .clang-format
Original file line number Diff line number Diff line change
Expand Up @@ -138,7 +138,6 @@ ReflowComments: true
RemoveBracesLLVM: false
SeparateDefinitionBlocks: Always
ShortNamespaceLines: 1
SortIncludes: CaseSensitive
SortJavaStaticImport: Before
SortUsingDeclarations: true
SpaceAfterCStyleCast: false
Expand Down
2 changes: 1 addition & 1 deletion .github/workflows/ubuntu-build.yml
Original file line number Diff line number Diff line change
Expand Up @@ -16,7 +16,7 @@ jobs:
BUILD_TYPE: [Debug,Release]
COMPILER: [gcc,clang]

name: Ubuntu-${{ matrix.BUILD_TYPE }}
name: Ubuntu-${{ matrix.BUILD_TYPE }}-${{matrix.COMPILER}}
runs-on: ${{ matrix.os }}

# Set up a global environment variable for build scripts
Expand Down
70 changes: 33 additions & 37 deletions core/DCache.hpp
Original file line number Diff line number Diff line change
Expand Up @@ -10,12 +10,15 @@
#include "cache/TreePLRUReplacement.hpp"
#include "MemoryAccessInfo.hpp"

namespace olympia {
class DCache : public sparta::Unit {
public:
class CacheParameterSet : public sparta::ParameterSet {
public:
CacheParameterSet(sparta::TreeNode *n) : sparta::ParameterSet(n) {}
namespace olympia
{
class DCache : public sparta::Unit
{
public:
class CacheParameterSet : public sparta::ParameterSet
{
public:
CacheParameterSet(sparta::TreeNode* n) : sparta::ParameterSet(n) {}

// Parameters for the DL1 cache
PARAMETER(uint32_t, l1_line_size, 64, "DL1 line size (power of 2)")
Expand All @@ -26,24 +29,24 @@ namespace olympia {
};

static const char name[];
DCache(sparta::TreeNode *n, const CacheParameterSet *p);
DCache(sparta::TreeNode* n, const CacheParameterSet* p);

private:
bool dataLookup_(const MemoryAccessInfoPtr &mem_access_info_ptr);
private:
bool dataLookup_(const MemoryAccessInfoPtr & mem_access_info_ptr);

void reloadCache_(uint64_t phy_addr);

void getInstsFromLSU_(const MemoryAccessInfoPtr &memory_access_info_ptr);
void getInstsFromLSU_(const MemoryAccessInfoPtr & memory_access_info_ptr);

void getAckFromL2Cache_(const uint32_t &ack);
void getAckFromL2Cache_(const uint32_t & ack);

void getRespFromL2Cache_(const InstPtr &inst_ptr);
void getRespFromL2Cache_(const InstPtr & inst_ptr);

using L1Handle = CacheFuncModel::Handle;
L1Handle l1_cache_;
const bool l1_always_hit_;
bool busy_;
uint32_t cache_latency_;
bool busy_ = false;
uint32_t cache_latency_ = 0;
// Keep track of the instruction that causes current outstanding cache miss
MemoryAccessInfoPtr cache_pending_inst_ = nullptr;

Expand All @@ -53,29 +56,25 @@ namespace olympia {
////////////////////////////////////////////////////////////////////////////////
// Input Ports
////////////////////////////////////////////////////////////////////////////////
sparta::DataInPort<MemoryAccessInfoPtr> in_lsu_lookup_req_
{&unit_port_set_, "in_lsu_lookup_req", 0};
sparta::DataInPort<MemoryAccessInfoPtr> in_lsu_lookup_req_{&unit_port_set_,
"in_lsu_lookup_req", 0};

sparta::DataInPort<uint32_t> in_l2cache_ack_
{&unit_port_set_, "in_l2cache_ack", 1};
sparta::DataInPort<uint32_t> in_l2cache_ack_{&unit_port_set_, "in_l2cache_ack", 1};

sparta::DataInPort<InstPtr> in_l2cache_resp_
{&unit_port_set_, "in_l2cache_resp", 1};
sparta::DataInPort<InstPtr> in_l2cache_resp_{&unit_port_set_, "in_l2cache_resp", 1};

////////////////////////////////////////////////////////////////////////////////
// Output Ports
////////////////////////////////////////////////////////////////////////////////
sparta::SignalOutPort out_lsu_free_req_
{&unit_port_set_, "out_lsu_free_req", 0};
sparta::SignalOutPort out_lsu_free_req_{&unit_port_set_, "out_lsu_free_req", 0};

sparta::DataOutPort<MemoryAccessInfoPtr> out_lsu_lookup_ack_
{&unit_port_set_, "out_lsu_lookup_ack", 0};
sparta::DataOutPort<MemoryAccessInfoPtr> out_lsu_lookup_ack_{&unit_port_set_,
"out_lsu_lookup_ack", 0};

sparta::DataOutPort<MemoryAccessInfoPtr> out_lsu_lookup_req_
{&unit_port_set_, "out_lsu_lookup_req", 1};
sparta::DataOutPort<MemoryAccessInfoPtr> out_lsu_lookup_req_{&unit_port_set_,
"out_lsu_lookup_req", 1};

sparta::DataOutPort<InstPtr> out_l2cache_req_
{&unit_port_set_, "out_l2cache_req", 0};
sparta::DataOutPort<InstPtr> out_l2cache_req_{&unit_port_set_, "out_l2cache_req", 0};

////////////////////////////////////////////////////////////////////////////////
// Events
Expand All @@ -84,15 +83,12 @@ namespace olympia {
////////////////////////////////////////////////////////////////////////////////
// Counters
////////////////////////////////////////////////////////////////////////////////
sparta::Counter dl1_cache_hits_{
getStatisticSet(), "dl1_cache_hits",
"Number of DL1 cache hits", sparta::Counter::COUNT_NORMAL
};
sparta::Counter dl1_cache_hits_{getStatisticSet(), "dl1_cache_hits",
"Number of DL1 cache hits", sparta::Counter::COUNT_NORMAL};

sparta::Counter dl1_cache_misses_{
getStatisticSet(), "dl1_cache_misses",
"Number of DL1 cache misses", sparta::Counter::COUNT_NORMAL
};
sparta::Counter dl1_cache_misses_{getStatisticSet(), "dl1_cache_misses",
"Number of DL1 cache misses",
sparta::Counter::COUNT_NORMAL};
};

}
} // namespace olympia
2 changes: 1 addition & 1 deletion core/Decode.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -84,7 +84,7 @@ namespace olympia
for(uint32_t i = 0; i < num_decode; ++i) {
const auto & inst = fetch_queue_.read(0);
insts->emplace_back(inst);
inst->setStatus(Inst::Status::RENAMED);
inst->setStatus(Inst::Status::DECODED);

ILOG("Decoded: " << inst);

Expand Down
6 changes: 6 additions & 0 deletions core/Inst.hpp
Original file line number Diff line number Diff line change
Expand Up @@ -114,6 +114,12 @@ namespace olympia
}

void setStatus(Status status) {
sparta_assert(status_state_ != status,
"Status being set twice to the same value: "
<< status << " " << *this);
sparta_assert(status > status_state_,
"Cannot go backwards in status. Current: "
<< status_state_ << " New: " << status << *this);
status_state_ = status;
if(getStatus() == Status::COMPLETED) {
if(ev_retire_ != 0) {
Expand Down
Loading

0 comments on commit 30b7961

Please sign in to comment.