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Vector 1.0 Support VALU #167

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merged 14 commits into from
Jul 1, 2024
Merged

Vector 1.0 Support VALU #167

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cd9b060
Pushing vector support for basic vadd.vv and vsub.vv, lmul, UOPs gene…
aarongchan May 6, 2024
3b43162
Removing CPUTopology.cpp clang formatting
aarongchan May 6, 2024
9091fd6
Cleaning up commented code
aarongchan May 6, 2024
c098650
New struct for Vector CSRs, vset updates, and valu adder width
aarongchan May 13, 2024
daaa41f
Moved vset stalling to fetch
aarongchan May 21, 2024
a9dd8fb
Fixed decode bug, UOps now increment counter for parent instead of lo…
aarongchan May 22, 2024
7840395
Testing fixed, cleanup and add vset wait to decode stage instead
aarongchan May 31, 2024
f1e309b
Merge branch 'master' into vector_1.0_support_basic
aarongchan Jun 10, 2024
5bff062
Merge remote-tracking branch 'origin/master' into vector_1.0_support_…
aarongchan Jun 11, 2024
41b2dfd
Fixing regression for most recent commits, code cleanup
aarongchan Jun 11, 2024
b8028a3
Addressing comments
aarongchan Jun 13, 2024
c8a223f
Fixing tail agnostic implementation and VL settings
aarongchan Jun 19, 2024
73ca9f4
Addressing comments, fixing vset conditional statements
aarongchan Jun 23, 2024
b336996
Setting LMUL to 1 when UOp fracturing
aarongchan Jun 23, 2024
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46 changes: 30 additions & 16 deletions arches/big_core.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -11,6 +11,7 @@ top.cpu.core0:
rename.params.num_to_rename: 8
rename.params.num_integer_renames: 64
rename.params.num_float_renames: 64
rename.params.num_vector_renames: 64
dispatch.params.num_to_dispatch: 8
rob.params.num_to_retire: 8
dcache.params:
Expand All @@ -32,7 +33,8 @@ top.cpu.core0.extension.core_extensions:
["float", "faddsub", "fmac"], # exe6
["float", "f2i"], # exe7
["br"], # exe8
["br"] # exe9
["br"], # exe9
["vint", "vset", "vdiv", "vmul"]
]
# this is used to set how many units per queue
# ["0", "3"] means iq0 has exe0, exe1, exe2, and exe3, so it's inclusive
Expand All @@ -47,25 +49,37 @@ top.cpu.core0.extension.core_extensions:
["2", "3"], # iq1 -> exe2, exe3
["4", "5"], # iq2 -> exe4, exe5
["6", "7"], # iq3 -> exe6, exe7
["8", "9"] # iq4 -> exe8, exe9
["8", "9"], # iq4 -> exe8, exe9
["10"] # iq5 -> exe10
]
top.cpu.core0.rename.scoreboards:
# From
# |
# V
integer.params.latency_matrix: |
[["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"],
["lsu", 1, 1, 1, 1, 1, 1],
["iq0", 1, 1, 1, 1, 1, 1],
["iq1", 1, 1, 1, 1, 1, 1],
["iq2", 1, 1, 1, 1, 1, 1],
["iq3", 1, 1, 1, 1, 1, 1],
["iq4", 1, 1, 1, 1, 1, 1]]
[["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"],
["lsu", 1, 1, 1, 1, 1, 1, 1],
["iq0", 1, 1, 1, 1, 1, 1, 1],
["iq1", 1, 1, 1, 1, 1, 1, 1],
["iq2", 1, 1, 1, 1, 1, 1, 1],
["iq3", 1, 1, 1, 1, 1, 1, 1],
["iq4", 1, 1, 1, 1, 1, 1, 1],
["iq5", 1, 1, 1, 1, 1, 1, 1]]
float.params.latency_matrix: |
[["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"],
["lsu", 1, 1, 1, 1, 1, 1],
["iq0", 1, 1, 1, 1, 1, 1],
["iq1", 1, 1, 1, 1, 1, 1],
["iq2", 1, 1, 1, 1, 1, 1],
["iq3", 1, 1, 1, 1, 1, 1],
["iq4", 1, 1, 1, 1, 1, 1]]
[["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"],
["lsu", 1, 1, 1, 1, 1, 1, 1],
["iq0", 1, 1, 1, 1, 1, 1, 1],
["iq1", 1, 1, 1, 1, 1, 1, 1],
["iq2", 1, 1, 1, 1, 1, 1, 1],
["iq3", 1, 1, 1, 1, 1, 1, 1],
["iq4", 1, 1, 1, 1, 1, 1, 1],
["iq5", 1, 1, 1, 1, 1, 1, 1]]
vector.params.latency_matrix: |
[["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"],
["lsu", 1, 1, 1, 1, 1, 1, 1],
["iq0", 1, 1, 1, 1, 1, 1, 1],
["iq1", 1, 1, 1, 1, 1, 1, 1],
["iq2", 1, 1, 1, 1, 1, 1, 1],
["iq3", 1, 1, 1, 1, 1, 1, 1],
["iq4", 1, 1, 1, 1, 1, 1, 1],
["iq5", 1, 1, 1, 1, 1, 1, 1]]
254 changes: 254 additions & 0 deletions arches/isa_json/olympia_uarch_rv64v.json
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Original file line number Diff line number Diff line change
@@ -0,0 +1,254 @@
[
{
"mnemonic": "vadd.vv",
"pipe" : "vint",
"latency" : 1
},
{
"mnemonic": "vadd.vx",
"pipe": "vint",
"latency": 1
},
{
"mnemonic": "vadd.vi",
"pipe": "vint",
"latency": 1
},
{
"mnemonic": "vsub.vv",
"pipe" : "vint",
"latency" : 1
},
{
"mnemonic": "vsub.vx",
"pipe" : "vint",
"latency" : 1
},
{
"mnemonic": "vrsub.vi",
"pipe" : "vint",
"latency" : 1
},
{
"mnemonic": "vrsub.vx",
"pipe" : "vint",
"latency" : 1
},
{
"mnemonic": "vsetvli",
"pipe": "vset",
"latency": 1
},
{
"mnemonic": "vsetvl",
"pipe": "vset",
"latency": 1
},
{
"mnemonic": "vsetivli",
"pipe": "vset",
"latency": 1
},
{
"mnemonic": "vmul.vv",
"pipe": "vmul",
"latency": 3
},
{
"mnemonic": "vmul.vx",
"pipe": "vmul",
"latency": 3
},
{
"mnemonic": "vmulhu.vx",
"pipe": "vmul",
"latency": 3
},
{
"mnemonic": "vmulhu.vv",
"pipe": "vmul",
"latency": 3
},
{
"mnemonic": "vmulh.vv",
"pipe": "vmul",
"latency": 3
},
{
"mnemonic": "vmulh.vx",
"pipe": "vmul",
"latency": 3
},
{
"mnemonic": "vmulhsu.vv",
"pipe": "vmul",
"latency": 3
},
{
"mnemonic": "vmulhsu.vx",
"pipe": "vmul",
"latency": 3
},
{
"mnemonic": "vdiv.vv",
"pipe": "vdiv",
"latency": 23
},
{
"mnemonic": "vdiv.vx",
"pipe": "vdiv",
"latency": 23
},
{
"mnemonic": "vdivu.vv",
"pipe": "vdiv",
"latency": 23
},
{
"mnemonic": "vdivu.vx",
"pipe": "vdiv",
"latency": 23
},
{
"mnemonic": "vremu.vv",
"pipe": "vdiv",
"latency": 23
},
{
"mnemonic": "vremu.vx",
"pipe": "vdiv",
"latency": 23
},
{
"mnemonic": "vrem.vv",
"pipe": "vdiv",
"latency": 23
},
{
"mnemonic": "vrem.vx",
"pipe": "vdiv",
"latency": 23
},
{
"mnemonic": "vwmul.vv",
"pipe": "vmul",
"latency": 3
},
{
"mnemonic": "vwmul.vx",
"pipe": "vmul",
"latency": 3
},
{
"mnemonic": "vwmulu.vv",
"pipe": "vmul",
"latency": 3
},
{
"mnemonic": "vwmulu.vx",
"pipe": "vmul",
"latency": 3
},
{
"mnemonic": "vwmulsu.vv",
"pipe": "vmul",
"latency": 3
},
{
"mnemonic": "vwmulsu.vx",
"pipe": "vmul",
"latency": 3
},
{
"mnemonic": "vwaddu.vv",
"pipe": "vint",
"latency": 1
},
{
"mnemonic": "vwaddu.vx",
"pipe": "vint",
"latency": 1
},
{
"mnemonic": "vwsubu.vv",
"pipe": "vint",
"latency": 1
},
{
"mnemonic": "vwsubu.vx",
"pipe": "vint",
"latency": 1
},
{
"mnemonic": "vwadd.vv",
"pipe": "vint",
"latency": 1
},
{
"mnemonic": "vwadd.vx",
"pipe": "vint",
"latency": 1
},
{
"mnemonic": "vwsub.vv",
"pipe": "vint",
"latency": 1
},
{
"mnemonic": "vwsub.vx",
"pipe": "vint",
"latency": 1
},
{
"mnemonic": "vwaddu.wv",
"pipe": "vint",
"latency": 1
},
{
"mnemonic": "vwaddu.wx",
"pipe": "vint",
"latency": 1
},
{
"mnemonic": "vwsubu.wv",
"pipe": "vint",
"latency": 1
},
{
"mnemonic": "vwsubu.wx",
"pipe": "vint",
"latency": 1
},
{
"mnemonic": "vwadd.wv",
"pipe": "vint",
"latency": 1
},
{
"mnemonic": "vwadd.wx",
"pipe": "vint",
"latency": 1
},
{
"mnemonic": "vwsub.wv",
"pipe": "vint",
"latency": 1
},
{
"mnemonic": "vwsub.wx",
"pipe": "vint",
"latency": 1
},
{
"mnemonic": "vsmul.vx",
"pipe": "vmul",
"latency": 3
},
{
"mnemonic": "vsmul.vv",
"pipe": "vmul",
"latency": 3
}


]
40 changes: 26 additions & 14 deletions arches/medium_core.yaml
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -26,7 +26,8 @@ top.cpu.core0.extension.core_extensions:
["int"], # exe2
["float", "faddsub", "fmac"], # exe3
["float", "f2i"], # exe4
["br"] # exe5
["br"], # exe5
["vint", "vset", "vdiv", "vmul"] # exe6
]

# this is used to set how many units per queue
Expand All @@ -40,24 +41,35 @@ top.cpu.core0.extension.core_extensions:
["0"], # iq0 -> exe0
["1", "2"], # iq1 -> exe1, exe2
["3", "4"], # iq2 -> exe3, exe4
["5"] # iq3 -> exe5
["5"], # iq3 -> exe5
["6"]
]

top.cpu.core0.rename.scoreboards:
# From
# |
# V
integer.params.latency_matrix: |
[["", "lsu", "iq0", "iq1", "iq2", "iq3"],
["lsu", 1, 1, 1, 1, 1],
["iq0", 1, 1, 1, 1, 1],
["iq1", 1, 1, 1, 1, 1],
["iq2", 1, 1, 1, 1, 1],
["iq3", 1, 1, 1, 1, 1]]
[["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"],
["lsu", 1, 1, 1, 1, 1, 1],
["iq0", 1, 1, 1, 1, 1, 1],
["iq1", 1, 1, 1, 1, 1, 1],
["iq2", 1, 1, 1, 1, 1, 1],
["iq3", 1, 1, 1, 1, 1, 1],
["iq4", 1, 1, 1, 1, 1, 1]]
float.params.latency_matrix: |
[["", "lsu", "iq0", "iq1", "iq2", "iq3"],
["lsu", 1, 1, 1, 1, 1],
["iq0", 1, 1, 1, 1, 1],
["iq1", 1, 1, 1, 1, 1],
["iq2", 1, 1, 1, 1, 1],
["iq3", 1, 1, 1, 1, 1]]
[["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"],
["lsu", 1, 1, 1, 1, 1, 1],
["iq0", 1, 1, 1, 1, 1, 1],
["iq1", 1, 1, 1, 1, 1, 1],
["iq2", 1, 1, 1, 1, 1, 1],
["iq3", 1, 1, 1, 1, 1, 1],
["iq4", 1, 1, 1, 1, 1, 1]]
vector.params.latency_matrix: |
[["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"],
["lsu", 1, 1, 1, 1, 1, 1],
["iq0", 1, 1, 1, 1, 1, 1],
["iq1", 1, 1, 1, 1, 1, 1],
["iq2", 1, 1, 1, 1, 1, 1],
["iq3", 1, 1, 1, 1, 1, 1],
["iq4", 1, 1, 1, 1, 1, 1]]
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