Vector 1.0 Support VALU #167
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Signed-off-by: Aaron Chan <[email protected]>
…basic Merging mavis csrrw bug fix
core/ExecutePipe.cpp
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| if (num_passes_needed_ == 0) | ||
| { | ||
| const uint32_t num_passes = | ||
| std::ceil((ex_inst->getVL() / ex_inst->getSEW()) / valu_adder_num_); |
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I think you mean VLEN here instead of VL. VL (vector length) is the number of elements that an instruction can process whereas VLEN is the size of the vector registers. So for example, if VLEN is 128 and SEW is 8 than a single vector uop contains 16 elements. For LMUL 1, the VL would be 16 but increasing the LMUL will multiply the VL. This code looks like it works, but the method names could be more clear.
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Changed to VLEN in 73ca9f4. Added a conditional that will use VL if it is less the VLEN/SEW.
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This is a lot of really great work @aarongchan! |
kathlenemagnus-mips
approved these changes
Jul 1, 2024
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@kathlenemagnus-mips I think you need to approve on your other account for me to be able to merge. |
kathlenemagnus
approved these changes
Jul 1, 2024
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PR Goals:
Implement basic vector support for VALU operations, UOp generation for LMUL > 1, and vset support. The goal in this stage to design all necessary components to support a vadd.vv instruction with varying LMUL and SEW values set.
Documentation:
#89 (comment)